Re: [PATCH 3/4] test: Add mode-switch test for nested svm

[Avi Kivity <avi@redhat.com>]

  On 08/02/2010 04:33 PM, Joerg Roedel wrote:
> Signed-off-by: Joerg Roedel<joerg.roedel@amd.com>
> ---
>   kvm/test/x86/cstart64.S |    5 ++
>   kvm/test/x86/svm.c      |  109 +++++++++++++++++++++++++++++++++++++++++++++++
>   kvm/test/x86/types.h    |   20 +++++++++
>   3 files changed, 134 insertions(+), 0 deletions(-)
>   create mode 100644 kvm/test/x86/types.h
>
> diff --git a/kvm/test/x86/cstart64.S b/kvm/test/x86/cstart64.S
> index f1a9d09..46e9d5c 100644
> --- a/kvm/test/x86/cstart64.S
> +++ b/kvm/test/x86/cstart64.S
> @@ -51,6 +51,11 @@ gdt64:
>   	.quad 0x00cf93000000ffff // 64-bit data segment
>   	.quad 0x00affb000000ffff // 64-bit code segment (user)
>   	.quad 0x00cff3000000ffff // 64-bit data segment (user)
> +	.quad 0x00cf9b000000ffff // 32-bit code segment
> +	.quad 0x00cf92000000ffff // 32-bit code segment
> +	.quad 0x008F9A000000FFFF // 16-bit code segment
> +	.quad 0x008F92000000FFFF // 16-bit data segment
> +
>   tss_descr:
>   	.rept max_cpus
>   	.quad 0x000089000000ffff // 64-bit avail tss
> diff --git a/kvm/test/x86/svm.c b/kvm/test/x86/svm.c
> index 4a7a662..fd98505 100644
> --- a/kvm/test/x86/svm.c
> +++ b/kvm/test/x86/svm.c
> @@ -4,6 +4,7 @@
>   #include "msr.h"
>   #include "vm.h"
>   #include "smp.h"
> +#include "types.h"
>
>   static void setup_svm(void)
>   {
> @@ -235,6 +236,112 @@ static bool check_next_rip(struct test *test)
>       return address == test->vmcb->control.next_rip;
>   }
>
> +static void prepare_mode_switch(struct test *test)
> +{
> +    test->vmcb->control.intercept_exceptions |= (1ULL<<  GP_VECTOR)
> +                                             |  (1ULL<<  UD_VECTOR)
> +                                             |  (1ULL<<  DF_VECTOR)
> +                                             |  (1ULL<<  PF_VECTOR);
> +    test->scratch = 0;
> +}
> +
> +static void test_mode_switch(struct test *test)
> +{
> +    asm volatile("	cli\n"
> +		 "	ljmp *1f\n" /* jump to 32-bit code segment */
> +		 "1:\n"
> +		 "	.long 2f\n"
> +		 "	.long 40\n"
> +		 ".code32\n"
> +		 "2:\n"
> +		 "	movl %%cr0, %%eax\n"
> +		 "	btcl  $31, %%eax\n" /* clear PG */
> +		 "	movl %%eax, %%cr0\n"
> +		 "	movl $0xc0000080, %%ecx\n" /* EFER */
> +		 "	rdmsr\n"
> +		 "	btcl $8, %%eax\n" /* clear LME */
> +		 "	wrmsr\n"
> +		 "	movl %%cr4, %%eax\n"
> +		 "	btcl $5, %%eax\n" /* clear PAE */
> +		 "	movl %%eax, %%cr4\n"
> +		 "	movw $64, %%ax\n"
> +		 "	movw %%ax, %%ds\n"
> +		 "	ljmpl $56, $3f\n" /* jump to 16 bit protected-mode */
> +		 ".code16\n"
> +		 "3:\n"
> +		 "	movl %%cr0, %%eax\n"
> +		 "	btcl $0, %%eax\n" /* clear PE  */
> +		 "	movl %%eax, %%cr0\n"
> +		 "	ljmpl $0, $4f\n"   /* jump to real-mode */
> +		 "4:\n"
> +		 "	vmmcall\n"
> +		 "	movl %%cr0, %%eax\n"
> +		 "	btsl $0, %%eax\n" /* set PE  */
> +		 "	movl %%eax, %%cr0\n"
> +		 "	ljmpl $40, $5f\n" /* back to protected mode */
> +		 ".code32\n"
> +		 "5:\n"
> +		 "	movl %%cr4, %%eax\n"
> +		 "	btsl $5, %%eax\n" /* set PAE */
> +		 "	movl %%eax, %%cr4\n"
> +		 "	movl $0xc0000080, %%ecx\n" /* EFER */
> +		 "	rdmsr\n"
> +		 "	btsl $8, %%eax\n" /* set LME */
> +		 "	wrmsr\n"
> +		 "	movl %%cr0, %%eax\n"
> +		 "	btsl  $31, %%eax\n" /* set PG */
> +		 "	movl %%eax, %%cr0\n"
> +		 "	ljmpl $8, $6f\n"    /* back to long mode */
> +		 ".code64\n\t"
> +		 "6:\n"
> +		 "	vmmcall\n"
> +		 ::: "rax", "rbx", "rcx", "rdx", "memory");
> +}
> +

What is this testing exactly?  There is no svm function directly 
associated with mode switch.  In fact, most L1s will intercept cr and 
efer access and emulate the mode switch, rather than letting L2 perform 
the mode switch directly.

So, it's testing that when cr and msr intercepts are disabled, those 
operations indeed aren't intercepted, and that writes to those registers 
are reflected in L1.  But this can be tested individually, like the cr3 
tests we already have, by picking a relatively unimportant bit (cr4.pge, 
cr0.ts) and playing with it with intercepts enabled and disabled.

-- 
error compiling committee.c: too many arguments to function