From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jin Dongming Subject: Re: [PATCH 2/2] reset mce registers of the given VCPU or all VCPUs with mce command. Date: Thu, 25 Nov 2010 17:46:09 +0900 Message-ID: <4CEE2251.2040400@np.css.fujitsu.com> References: <4CEDB9FA.5000400@np.css.fujitsu.com> <1290664558.2903.317.camel@yhuang-dev> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Cc: Avi Kivity , Marcelo Tosatti , Andi Kleen , Dean Nelson , Hidetoshi Seto , KVM list To: Huang Ying Return-path: Received: from fgwmail5.fujitsu.co.jp ([192.51.44.35]:38038 "EHLO fgwmail5.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751681Ab0KYIoE (ORCPT ); Thu, 25 Nov 2010 03:44:04 -0500 Received: from m4.gw.fujitsu.co.jp ([10.0.50.74]) by fgwmail5.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id oAP8i39c013210 for (envelope-from jin.dongming@np.css.fujitsu.com); Thu, 25 Nov 2010 17:44:03 +0900 Received: from smail (m4 [127.0.0.1]) by outgoing.m4.gw.fujitsu.co.jp (Postfix) with ESMTP id 8863345DE6E for ; Thu, 25 Nov 2010 17:44:03 +0900 (JST) Received: from s4.gw.fujitsu.co.jp (s4.gw.fujitsu.co.jp [10.0.50.94]) by m4.gw.fujitsu.co.jp (Postfix) with ESMTP id 68E7645DE4D for ; Thu, 25 Nov 2010 17:44:03 +0900 (JST) Received: from s4.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s4.gw.fujitsu.co.jp (Postfix) with ESMTP id 413291DB803A for ; Thu, 25 Nov 2010 17:44:03 +0900 (JST) Received: from m005.s.css.fujitsu.com (m005.s.css.fujitsu.com [10.23.4.35]) by s4.gw.fujitsu.co.jp (Postfix) with ESMTP id 000701DB8037 for ; Thu, 25 Nov 2010 17:44:02 +0900 (JST) In-Reply-To: <1290664558.2903.317.camel@yhuang-dev> Sender: kvm-owner@vger.kernel.org List-ID: Hi, Huang-san (2010/11/25 14:55), Huang Ying wrote: > On Thu, 2010-11-25 at 09:20 +0800, Jin Dongming wrote: >> --- a/monitor.c >> +++ b/monitor.c >> @@ -60,6 +60,7 @@ >> #include "trace.h" >> #endif >> #include "qemu-kvm.h" >> +#include "kvm_x86.h" >> >> //#define DEBUG >> //#define DEBUG_COMPLETION >> @@ -2277,7 +2278,19 @@ static void do_inject_mce(Monitor *mon, const QDict *qdict) >> #endif >> >> for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) { >> - if (cenv->cpu_index == cpu_index && cenv->mcg_cap) { >> + if (!cenv->mcg_cap) >> + continue; >> + >> +#if defined(KVM_CAP_MCE) >> + if (!status && !mcg_status) { >> + if (cenv->cpu_index == cpu_index || broadcast) >> + kvm_inject_x86_mce(cenv, 0, 0, 0, 0, 0, 0); >> + >> + continue; >> + } >> +#endif >> + >> + if (cenv->cpu_index == cpu_index) { >> cpu_inject_x86_mce(cenv, bank, status, mcg_status, addr, misc); >> #if defined(KVM_CAP_MCE) >> if (broadcast) > > Are you sure there is no test cases that require the Machine Check > registers not cleared? I have had a test case before that injects > another MCE when MCIP in MCGSTATUS is set to check whether system will > go reset. > > It may be better to clear MC registers in an explicit mode. MC registers could be cleared in Guest OS with APL. So I will cancel this patch. I will resend the patch for broadcast option. Best Regards, Jin Dongming > > Best Regards, > Huang Ying > > > -- > To unsubscribe from this list: send the line "unsubscribe kvm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > >