From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jin Dongming Subject: [PATCH 1/3] Clean up cpu_inject_x86_mce(). Date: Tue, 30 Nov 2010 17:12:32 +0900 Message-ID: <4CF4B1F0.2060206@np.css.fujitsu.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-2022-JP Content-Transfer-Encoding: 7bit Cc: Andi Kleen , Huang Ying , Hidetoshi Seto , Dean Nelson , KVM list To: Avi Kivity , Marcelo Tosatti Return-path: Received: from fgwmail6.fujitsu.co.jp ([192.51.44.36]:51193 "EHLO fgwmail6.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754236Ab0K3IK0 (ORCPT ); Tue, 30 Nov 2010 03:10:26 -0500 Received: from m5.gw.fujitsu.co.jp ([10.0.50.75]) by fgwmail6.fujitsu.co.jp (Fujitsu Gateway) with ESMTP id oAU8AOjs028576 for (envelope-from jin.dongming@np.css.fujitsu.com); Tue, 30 Nov 2010 17:10:24 +0900 Received: from smail (m5 [127.0.0.1]) by outgoing.m5.gw.fujitsu.co.jp (Postfix) with ESMTP id 10DEC45DE5A for ; Tue, 30 Nov 2010 17:10:24 +0900 (JST) Received: from s5.gw.fujitsu.co.jp (s5.gw.fujitsu.co.jp [10.0.50.95]) by m5.gw.fujitsu.co.jp (Postfix) with ESMTP id 9140D45DE51 for ; Tue, 30 Nov 2010 17:10:23 +0900 (JST) Received: from s5.gw.fujitsu.co.jp (localhost.localdomain [127.0.0.1]) by s5.gw.fujitsu.co.jp (Postfix) with ESMTP id 58D9D1DB803C for ; Tue, 30 Nov 2010 17:10:23 +0900 (JST) Received: from m004.s.css.fujitsu.com (m004.s.css.fujitsu.com [10.23.4.34]) by s5.gw.fujitsu.co.jp (Postfix) with ESMTP id 9756B1DB805D for ; Tue, 30 Nov 2010 17:10:21 +0900 (JST) Sender: kvm-owner@vger.kernel.org List-ID: Clean up cpu_inject_x86_mce() for later patch. Signed-off-by: Jin Dongming --- target-i386/helper.c | 26 ++++++++++++++++---------- 1 files changed, 16 insertions(+), 10 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index f5c06a8..e384fdc 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1023,21 +1023,12 @@ static void breakpoint_handler(CPUState *env) /* This should come from sysemu.h - if we could include it here... */ void qemu_system_reset_request(void); -void cpu_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, +static void qemu_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, uint64_t mcg_status, uint64_t addr, uint64_t misc) { uint64_t mcg_cap = cenv->mcg_cap; - unsigned bank_num = mcg_cap & 0xff; uint64_t *banks = cenv->mce_banks; - if (bank >= bank_num || !(status & MCI_STATUS_VAL)) - return; - - if (kvm_enabled()) { - kvm_inject_x86_mce(cenv, bank, status, mcg_status, addr, misc, 0); - return; - } - /* * if MSR_MCG_CTL is not all 1s, the uncorrected error * reporting is disabled @@ -1078,6 +1069,21 @@ void cpu_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, } else banks[1] |= MCI_STATUS_OVER; } + +void cpu_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, + uint64_t mcg_status, uint64_t addr, uint64_t misc) +{ + unsigned bank_num = cenv->mcg_cap & 0xff; + + if (bank >= bank_num || !(status & MCI_STATUS_VAL)) + return; + + if (kvm_enabled()) { + kvm_inject_x86_mce(cenv, bank, status, mcg_status, addr, misc, 0); + } else { + qemu_inject_x86_mce(cenv, bank, status, mcg_status, addr, misc); + } +} #endif /* !CONFIG_USER_ONLY */ static void mce_init(CPUX86State *cenv) -- 1.7.1.1