From: Avi Kivity <avi@redhat.com>
To: "Nadav Har'El" <nyh@il.ibm.com>
Cc: kvm@vger.kernel.org, gleb@redhat.com
Subject: Re: [PATCH 05/29] nVMX: Implement reading and writing of VMX MSRs
Date: Sun, 30 Jan 2011 11:52:32 +0200 [thread overview]
Message-ID: <4D4534E0.7010500@redhat.com> (raw)
In-Reply-To: <201101270832.p0R8WOxe002432@rice.haifa.ibm.com>
On 01/27/2011 10:32 AM, Nadav Har'El wrote:
> When the guest can use VMX instructions (when the "nested" module option is
> on), it should also be able to read and write VMX MSRs, e.g., to query about
> VMX capabilities. This patch adds this support.
>
>
> +#define CORE2_PINBASED_CTLS_MUST_BE_ONE 0x00000016
> + case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
> + case MSR_IA32_VMX_PINBASED_CTLS:
> + vmx_msr_low = CORE2_PINBASED_CTLS_MUST_BE_ONE;
> + vmx_msr_high = CORE2_PINBASED_CTLS_MUST_BE_ONE |
> + PIN_BASED_EXT_INTR_MASK |
> + PIN_BASED_NMI_EXITING |
> + PIN_BASED_VIRTUAL_NMIS;
Can we actually support PIN_BASED_VIRTUAL_NMIs on hosts which don't
support them?
Maybe better to drop for the initial version.
> + rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
> +
> + vmx_msr_low = 0; /* allow disabling any feature */
> + vmx_msr_high&= /* do not expose new untested features */
> + CPU_BASED_HLT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
> + CPU_BASED_CR3_STORE_EXITING | CPU_BASED_USE_IO_BITMAPS |
> + CPU_BASED_MOV_DR_EXITING | CPU_BASED_USE_TSC_OFFSETING |
> + CPU_BASED_MWAIT_EXITING | CPU_BASED_MONITOR_EXITING |
> + CPU_BASED_INVLPG_EXITING | CPU_BASED_TPR_SHADOW |
> +#ifdef CONFIG_X86_64
> + CPU_BASED_CR8_LOAD_EXITING |
> + CPU_BASED_CR8_STORE_EXITING |
> +#endif
> + CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
Similarly, I think CPU_BASED_TPR_SHADOW and
CPU_BASED_ACTIVATE_SECONDARY_CONTROLS are not available on all models.
> + case MSR_IA32_VMX_PROCBASED_CTLS2:
> + *pdata = 0;
> + if (vm_need_virtualize_apic_accesses(vcpu->kvm))
> + *pdata |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
> + break;
Here, at least you qualify support by checking the host.
> + case MSR_IA32_VMX_EPT_VPID_CAP:
> + /* Currently, no nested ept or nested vpid */
> + *pdata = 0;
> + break;
> + default:
> + return 0;
> + }
> +
> + return 1;
> +}
> +
> +static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
> +{
> + if (!nested_vmx_allowed(vcpu))
> + return 0;
> +
> + /*
> + * according to the spec, "VMX capability MSRs are read-only; an
> + * attempt to write them (with WRMSR) produces a #GP(0).
> + */
> + if (msr_index>= MSR_IA32_VMX_BASIC&&
> + msr_index<= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
> + kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
> + return 1;
Can just drop this part, #GP is the default response.
> + } else if (msr_index == MSR_IA32_FEATURE_CONTROL)
> + /* TODO: the right thing. */
> + return 1;
> + else
> + return 0;
> +}
--
error compiling committee.c: too many arguments to function
next prev parent reply other threads:[~2011-01-30 9:52 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-01-27 8:29 [PATCH 0/29] nVMX: Nested VMX, v8 Nadav Har'El
2011-01-27 8:30 ` [PATCH 01/29] nVMX: Add "nested" module option to vmx.c Nadav Har'El
2011-01-27 8:30 ` [PATCH 02/29] nVMX: Implement VMXON and VMXOFF Nadav Har'El
2011-01-27 8:31 ` [PATCH 03/29] nVMX: Allow setting the VMXE bit in CR4 Nadav Har'El
2011-01-27 8:31 ` [PATCH 04/29] nVMX: Introduce vmcs12: a VMCS structure for L1 Nadav Har'El
2011-01-27 8:32 ` [PATCH 05/29] nVMX: Implement reading and writing of VMX MSRs Nadav Har'El
2011-01-30 9:52 ` Avi Kivity [this message]
2011-01-31 8:57 ` Nadav Har'El
2011-01-31 9:01 ` Avi Kivity
2011-01-27 8:32 ` [PATCH 06/29] nVMX: Decoding memory operands of VMX instructions Nadav Har'El
2011-01-27 8:33 ` [PATCH 07/29] nVMX: Hold a vmcs02 for each vmcs12 Nadav Har'El
2011-01-30 10:02 ` Avi Kivity
2011-01-31 9:26 ` Nadav Har'El
2011-01-31 9:41 ` Avi Kivity
2011-02-03 12:57 ` Nadav Har'El
2011-02-06 9:16 ` Avi Kivity
2011-02-13 13:04 ` Nadav Har'El
2011-02-13 14:58 ` Avi Kivity
2011-02-13 20:07 ` Nadav Har'El
2011-01-27 8:33 ` [PATCH 08/29] nVMX: Fix local_vcpus_link handling Nadav Har'El
2011-01-30 10:08 ` Avi Kivity
2011-01-27 8:34 ` [PATCH 09/29] nVMX: Add VMCS fields to the vmcs12 Nadav Har'El
2011-01-30 10:10 ` Avi Kivity
2011-01-27 8:34 ` [PATCH 10/29] nVMX: Success/failure of VMX instructions Nadav Har'El
2011-01-27 8:35 ` [PATCH 11/29] nVMX: Implement VMCLEAR Nadav Har'El
2011-01-30 12:07 ` Avi Kivity
2011-01-27 8:35 ` [PATCH 12/29] nVMX: Implement VMPTRLD Nadav Har'El
2011-01-27 8:36 ` [PATCH 13/29] nVMX: Implement VMPTRST Nadav Har'El
2011-01-27 8:37 ` [PATCH 14/29] nVMX: Implement VMREAD and VMWRITE Nadav Har'El
2011-01-27 8:37 ` [PATCH 15/29] nVMX: Prepare vmcs02 from vmcs01 and vmcs12 Nadav Har'El
2011-01-27 8:38 ` [PATCH 16/29] nVMX: Move register-syncing to a function Nadav Har'El
2011-01-27 8:38 ` [PATCH 17/29] nVMX: Implement VMLAUNCH and VMRESUME Nadav Har'El
2011-01-27 8:39 ` [PATCH 18/29] nVMX: No need for handle_vmx_insn function any more Nadav Har'El
2011-01-27 8:39 ` [PATCH 19/29] nVMX: Exiting from L2 to L1 Nadav Har'El
2011-01-27 8:40 ` [PATCH 20/29] nVMX: Deciding if L0 or L1 should handle an L2 exit Nadav Har'El
2011-01-27 8:40 ` [PATCH 21/29] nVMX: Correct handling of interrupt injection Nadav Har'El
2011-01-27 8:41 ` [PATCH 22/29] nVMX: Correct handling of exception injection Nadav Har'El
2011-01-27 8:41 ` [PATCH 23/29] nVMX: Correct handling of idt vectoring info Nadav Har'El
2011-01-27 8:42 ` [PATCH 24/29] nVMX: Handling of CR0 and CR4 modifying instructions Nadav Har'El
2011-01-27 8:42 ` [PATCH 25/29] nVMX: Further fixes for lazy FPU loading Nadav Har'El
2011-01-27 8:43 ` [PATCH 26/29] nVMX: Additional TSC-offset handling Nadav Har'El
2011-01-27 8:43 ` [PATCH 27/29] nVMX: Add VMX to list of supported cpuid features Nadav Har'El
2011-01-27 8:44 ` [PATCH 28/29] nVMX: Miscellenous small corrections Nadav Har'El
2011-01-27 8:44 ` [PATCH 29/29] nVMX: Documentation Nadav Har'El
2011-01-28 8:41 ` [PATCH 0/29] nVMX: Nested VMX, v8 Juerg Haefliger
2011-01-28 17:16 ` Nadav Har'El
2011-01-31 10:07 ` Nadav Har'El
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