From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: Re: [Patch v4 2/4] Add SMEP handling when setting CR4 Date: Tue, 31 May 2011 21:05:35 +0300 Message-ID: <4DE52DEF.2000009@redhat.com> References: <5D8008F58939784290FAB48F5497519844E9278011@shsmsx502.ccr.corp.intel.com> <20110531175232.GA2721@amt.cnet> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: "Yang, Wei Y" , "kvm@vger.kernel.org" To: Marcelo Tosatti Return-path: Received: from mx1.redhat.com ([209.132.183.28]:17916 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758036Ab1EaSFk (ORCPT ); Tue, 31 May 2011 14:05:40 -0400 In-Reply-To: <20110531175232.GA2721@amt.cnet> Sender: kvm-owner@vger.kernel.org List-ID: On 05/31/2011 08:52 PM, Marcelo Tosatti wrote: > On Sun, May 29, 2011 at 07:41:57PM +0800, Yang, Wei Y wrote: > > This patch adds SMEP handling when setting CR4. > > > > Signed-off-by: Yang, Wei > > Signed-off-by: Shan, Haitao > > Signed-off-by: Li, Xin > > > > --- > > arch/x86/kvm/x86.c | 15 +++++++++++++-- > > 1 files changed, 13 insertions(+), 2 deletions(-) > > > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > > index 77c9d86..91bfc40 100644 > > --- a/arch/x86/kvm/x86.c > > +++ b/arch/x86/kvm/x86.c > > @@ -579,6 +579,14 @@ static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu) > > return best&& (best->ecx& bit(X86_FEATURE_XSAVE)); > > } > > > > +static bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu) > > +{ > > + struct kvm_cpuid_entry2 *best; > > + > > + best = kvm_find_cpuid_entry(vcpu, 7, 0); > > + return best&& (best->ebx& bit(X86_FEATURE_SMEP)); > > +} > > + > > static void update_cpuid(struct kvm_vcpu *vcpu) > > { > > struct kvm_cpuid_entry2 *best; > > @@ -598,14 +606,17 @@ static void update_cpuid(struct kvm_vcpu *vcpu) > > int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) > > { > > unsigned long old_cr4 = kvm_read_cr4(vcpu); > > - unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE; > > - > > + unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | > > + X86_CR4_PAE | X86_CR4_SMEP; > > if (cr4& CR4_RESERVED_BITS) > > return 1; > > > > if (!guest_cpuid_has_xsave(vcpu)&& (cr4& X86_CR4_OSXSAVE)) > > return 1; > > > > + if (!guest_cpuid_has_smep(vcpu)&& (cr4& X86_CR4_SMEP)) > > + return 1; > > + > > if (is_long_mode(vcpu)) { > > if (!(cr4& X86_CR4_PAE)) > > return 1; > > A new field in vcpu->arch.mmu.base_role for smep is required > for shadow MMU (similar to nxe). I plan to add that with my cr0.wp=0 fixup (it's only needed there, right?) -- I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain.