From: Avi Kivity <avi@redhat.com>
To: Marcelo Tosatti <mtosatti@redhat.com>
Cc: "Yang, Wei Y" <wei.y.yang@intel.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Subject: Re: [Patch v4 2/4] Add SMEP handling when setting CR4
Date: Tue, 31 May 2011 22:03:26 +0300 [thread overview]
Message-ID: <4DE53B7E.4070403@redhat.com> (raw)
In-Reply-To: <20110531184827.GA4376@amt.cnet>
On 05/31/2011 09:48 PM, Marcelo Tosatti wrote:
> On Tue, May 31, 2011 at 09:05:35PM +0300, Avi Kivity wrote:
> > >> if (is_long_mode(vcpu)) {
> > >> if (!(cr4& X86_CR4_PAE))
> > >> return 1;
> > >
> > >A new field in vcpu->arch.mmu.base_role for smep is required
> > >for shadow MMU (similar to nxe).
> >
> > I plan to add that with my cr0.wp=0 fixup (it's only needed there, right?)
>
> Sptes instantiated when cr4.smep = 0 should not be used when cr4.smep =
> 1, so no (unlikely that guest kernel executes user=1 code anyway, but
> for consistency with other base_role flags).
Why not? The sptes are interpreted exactly the same.
sptes are interpreted differently when efer.nxe=1 - if bit 63 is set, it
will fault when nxe=0 and will not fault when nxe=1 (for non-fetch
accesses). So we can't share those sptes.
> OK then, you'll fix that.
>
Sure. I'll post the patches as soon as this hits 'next'.
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
next prev parent reply other threads:[~2011-05-31 19:03 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-29 11:41 [Patch v4 2/4] Add SMEP handling when setting CR4 Yang, Wei Y
2011-05-31 17:52 ` Marcelo Tosatti
2011-05-31 18:05 ` Avi Kivity
2011-05-31 18:48 ` Marcelo Tosatti
2011-05-31 19:03 ` Avi Kivity [this message]
2011-06-01 12:32 ` Marcelo Tosatti
2011-06-01 12:36 ` Avi Kivity
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