From: Avi Kivity <avi@redhat.com>
To: "Yang, Wei" <wei.y.yang@intel.com>
Cc: kvm@vger.kernel.org, the arch/x86 maintainers <x86@kernel.org>
Subject: Re: [PATCH 0/3] Enable RDWRGSFS feature support for KVM
Date: Tue, 14 Jun 2011 15:30:56 +0300 [thread overview]
Message-ID: <4DF75480.2040900@redhat.com> (raw)
In-Reply-To: <1308053419-9953-1-git-send-email-wei.y.yang@intel.com>
On 06/14/2011 03:10 PM, Yang, Wei wrote:
> This patch enalbes RDWRGSFS feature to KVM guests.
>
> Write/read FS/GS base instructions enable user level code
> to read/write FS& GS segment base registers for thread
> local storage.
>
Patches look good, but something appears missing - usually when an
instruction is enabled by a cr4 bit, there is an additional cpuid bit
that gets turned on, so userspace can tell if it is safe to use the
instruction. Is it not the case here?
Unrelated: what about enabling it for host userspace? You'll need to
modify IST interrupt entry points (NMI/MCE etc) not to look at the value
of gsbase, but it shouldn't be too difficult.
--
error compiling committee.c: too many arguments to function
next prev parent reply other threads:[~2011-06-14 12:31 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-14 12:10 [PATCH 0/3] Enable RDWRGSFS feature support for KVM Yang, Wei
2011-06-14 12:10 ` [PATCH 1/3] Remove RDWRGSFS bit from CR4_RESERVED_BITS Yang, Wei
2011-06-14 12:10 ` [PATCH 2/3] Add RDWRGSFS support when setting CR4 Yang, Wei
2011-06-14 12:10 ` [PATCH 3/3] Expose RDWRGSFS bit to KVM guests Yang, Wei
2011-06-14 12:30 ` Avi Kivity [this message]
2011-06-14 12:40 ` [PATCH 0/3] Enable RDWRGSFS feature support for KVM Avi Kivity
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