[PATCH 0/3] Enable RDWRGSFS feature support for KVM

[PATCH 0/3] Enable RDWRGSFS feature support for KVM

[Yang, Wei]

This patch enalbes RDWRGSFS feature to KVM guests.

Write/read FS/GS base instructions enable user level code
to read/write FS & GS segment base registers for thread
local storage.

 Signed-off-by: Yang, Wei <wei.y.yang@intel.com>

---
 arch/x86/include/asm/kvm_host.h        |    2 +-
 arch/x86/include/asm/processor-flags.h |    1 +
 arch/x86/kvm/x86.c                     |   13 ++++++++++++-
 3 files changed, 14 insertions(+), 2 deletions(-)

[PATCH 1/3] Remove RDWRGSFS bit from CR4_RESERVED_BITS

[Yang, Wei]

This patch removes RDWRGSFS bit from CR4_RESERVED_BITS.

 Signed-off-by: Yang, Wei <wei.y.yang@intel.com>

---
 arch/x86/include/asm/kvm_host.h        |    2 +-
 arch/x86/include/asm/processor-flags.h |    1 +
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index fc38eca..554be45 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -48,7 +48,7 @@
 	(~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
 			  | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE     \
 			  | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR  \
-			  | X86_CR4_OSXSAVE | X86_CR4_SMEP              \
+			  | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_RDWRGSFS \
 			  | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
 
 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h
index 59ab4df..2dddb31 100644
--- a/arch/x86/include/asm/processor-flags.h
+++ b/arch/x86/include/asm/processor-flags.h
@@ -59,6 +59,7 @@
 #define X86_CR4_OSFXSR	0x00000200 /* enable fast FPU save and restore */
 #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
 #define X86_CR4_VMXE	0x00002000 /* enable VMX virtualization */
+#define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */
 #define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
 #define X86_CR4_SMEP	0x00100000 /* enable SMEP support */
 
-- 
1.7.1

[PATCH 2/3] Add RDWRGSFS support when setting CR4

[Yang, Wei]

This patch adds RDWRGSFS support when setting CR4.

  Signed-off-by: Yang, Wei <wei.y.yang@intel.com>

---
 arch/x86/kvm/x86.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index ff4623b..59d25ce 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -588,6 +588,14 @@ static bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu)
 	return best && (best->ebx & bit(X86_FEATURE_SMEP));
 }
 
+static bool guest_cpuid_has_fsgsbase(struct kvm_vcpu *vcpu)
+{
+	struct kvm_cpuid_entry2 *best;
+
+	best = kvm_find_cpuid_entry(vcpu, 7, 0);
+	return best && (best->ebx & bit(X86_FEATURE_FSGSBASE));
+}
+
 static void update_cpuid(struct kvm_vcpu *vcpu)
 {
 	struct kvm_cpuid_entry2 *best;
@@ -618,6 +626,9 @@ int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 	if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
 		return 1;
 
+	if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
+		return 1;
+
 	if (is_long_mode(vcpu)) {
 		if (!(cr4 & X86_CR4_PAE))
 			return 1;
-- 
1.7.1

[PATCH 3/3] Expose RDWRGSFS bit to KVM guests

[Yang, Wei]

This patch exposes RDWRGSFS bit to KVM guests.

 Signed-off-by: Yang, Wei <wei.y.yang@intel.com>

---
 arch/x86/kvm/x86.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 59d25ce..357e63a 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -2372,7 +2372,7 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 
 	/* cpuid 7.0.ebx */
 	const u32 kvm_supported_word9_x86_features =
-		F(SMEP);
+		F(SMEP) | F(FSGSBASE);
 
 	/* all calls to cpuid_count() should be made on the same cpu */
 	get_cpu();
-- 
1.7.1

Re: [PATCH 0/3] Enable RDWRGSFS feature support for KVM

[Avi Kivity]

On 06/14/2011 03:10 PM, Yang, Wei wrote:
> This patch enalbes RDWRGSFS feature to KVM guests.
>
> Write/read FS/GS base instructions enable user level code
> to read/write FS&  GS segment base registers for thread
> local storage.
>

Patches look good, but something appears missing - usually when an 
instruction is enabled by a cr4 bit, there is an additional cpuid bit 
that gets turned on, so userspace can tell if it is safe to use the 
instruction.  Is it not the case here?

Unrelated: what about enabling it for host userspace?  You'll need to 
modify IST interrupt entry points (NMI/MCE etc) not to look at the value 
of gsbase, but it shouldn't be too difficult.

-- 
error compiling committee.c: too many arguments to function

Re: [PATCH 0/3] Enable RDWRGSFS feature support for KVM

[Avi Kivity]

On 06/14/2011 03:30 PM, Avi Kivity wrote:
> On 06/14/2011 03:10 PM, Yang, Wei wrote:
>> This patch enalbes RDWRGSFS feature to KVM guests.
>>
>> Write/read FS/GS base instructions enable user level code
>> to read/write FS&  GS segment base registers for thread
>> local storage.
>>
>
> Patches look good, but something appears missing - usually when an 
> instruction is enabled by a cr4 bit, there is an additional cpuid bit 
> that gets turned on, so userspace can tell if it is safe to use the 
> instruction.  Is it not the case here?

I found it in the AVX2 spec, and it appears there is no such bit.  How 
is userspace supposed to know if it can use the instruction or not?

Anyway, patches applied, thanks.

-- 
error compiling committee.c: too many arguments to function