From mboxrd@z Thu Jan  1 00:00:00 1970
From: Anthony Liguori <anthony@codemonkey.ws>
Subject: Re: [Qemu-devel] [RFC v5 86/86] 440fx: fix PAM, PCI holes
Date: Mon, 25 Jul 2011 08:32:31 -0500
Message-ID: <4E2D706F.1030709@codemonkey.ws>
References: <1311180636-17012-1-git-send-email-avi@redhat.com> <1311180636-17012-87-git-send-email-avi@redhat.com> <4E2D6A97.9050606@codemonkey.ws> <4E2D6C45.5030308@redhat.com> <20110725131728.GD4404@redhat.com> <4E2D6F6C.5070301@redhat.com>
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Cc: Gleb Natapov <gleb@redhat.com>, qemu-devel@nongnu.org,
	kvm@vger.kernel.org
To: Avi Kivity <avi@redhat.com>
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On 07/25/2011 08:28 AM, Avi Kivity wrote:
> On 07/25/2011 04:17 PM, Gleb Natapov wrote:
>> On Mon, Jul 25, 2011 at 04:14:45PM +0300, Avi Kivity wrote:
>> > On 07/25/2011 04:07 PM, Anthony Liguori wrote:
>> > >On 07/20/2011 11:50 AM, Avi Kivity wrote:
>> > >>The current implementation of PAM and the PCI holes is broken in
>> several
>> > >>ways:
>> > >>
>> > >> - PCI BARs are not restricted to the PCI hole (a BAR may hide
>> memory)
>> > >
>> > >Technically, a BAR can be mapped to any non-RAM memory location.
>> >
>> > I understood TOM (Top Of Memory) to be fixed - can't find a regist=
er
>> > for it - but maybe I misread the spec.
>> >
>> PIIX3 spec:
>>
>> 2.2.11. TOM=97TOP OF MEMORY REGISTER (Function 0)
>> Address Offset: 69h
>> Default Value: 02h
>> Attribute: Read/Write
>>
>
> What's it doing in PIIX3? Is it the same TOM?

This is a programmable register used to indicate the TOM for the=20
purposes of forwarding ISA DMA transactions.

It is unrelated to the I440FX notion of top of memory.

Regards,

Anthony Liguori

>