From mboxrd@z Thu Jan 1 00:00:00 1970 From: Xiao Guangrong Subject: Re: [PATCH 10/11] KVM: MMU: fix detecting misaligned accessed Date: Wed, 27 Jul 2011 18:10:33 +0800 Message-ID: <4E2FE419.2010800@cn.fujitsu.com> References: <4E2EA3DB.7040403@cn.fujitsu.com> <4E2EA5AA.2010708@cn.fujitsu.com> <4E2FD731.7010206@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Cc: Marcelo Tosatti , LKML , KVM To: Avi Kivity Return-path: Received: from cn.fujitsu.com ([222.73.24.84]:51913 "EHLO song.cn.fujitsu.com" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1750982Ab1G0KIe (ORCPT ); Wed, 27 Jul 2011 06:08:34 -0400 In-Reply-To: <4E2FD731.7010206@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: On 07/27/2011 05:15 PM, Avi Kivity wrote: > On 07/26/2011 02:31 PM, Xiao Guangrong wrote: >> Sometimes, we only modify the last one byte of a pte to update status bit, >> for example, clear_bit is used to clear r/w bit in linux kernel and 'andb' >> instruction is used in this function, in this case, kvm_mmu_pte_write will >> treat it as misaligned access, and the shadow page table is zapped >> >> @@ -3597,6 +3597,14 @@ static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, >> >> offset = offset_in_page(gpa); >> pte_size = sp->role.cr4_pae ? 8 : 4; >> + >> + /* >> + * Sometimes, the OS only writes the last one bytes to update status >> + * bits, for example, in linux, andb instruction is used in clear_bit(). >> + */ >> + if (sp->role.level == 1&& !(offset& (pte_size - 1))&& bytes == 1) >> + return false; >> + > > Could be true for level > 1, no? > In my origin mind, i thought one-byte-instruction is usually used to update the last pte, but we do better remove this restriction. Will fix it in the next version, thanks!