From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marc Zyngier <marc.zyngier@arm.com>
Subject: Re: [Android-virt] [PATCH v5 11/13] ARM: KVM: Support SMP hosts
Date: Tue, 13 Dec 2011 14:17:33 +0000
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Cc: Avi Kivity <avi@redhat.com>,
	"tech@virtualopensystems.com" <tech@virtualopensystems.com>,
	"android-virt@lists.cs.columbia.edu"
	<android-virt@lists.cs.columbia.edu>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>
To: Christoffer Dall <c.dall@virtualopensystems.com>
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On 13/12/11 13:36, Christoffer Dall wrote:
> On Tue, Dec 13, 2011 at 4:37 AM, Avi Kivity <avi@redhat.com> wrote:
>>  if (new_virt_intr == IRQ | FIQ && virt_intr == FIQ) {
>>      /* IRQ raised, FIQ already set */
>>      return;
>>  }
>>
> 
> hmm, so what you want to avoid here is sending an IPI to the other CPU
> in case we already have FIQ raised? But I think we have to do this
> anyhow. If a guest is servicing a raised FIQ and have FIQs masked, but
> the GIC hasn't lowered the FIQ line yet, and now comes an IRQ, if the
> IRQ is unmasked we want to change the hypervisor virtual IRQ register
> right away as to signal an IRQ immediately and if the guest masks IRQ
> we still want to change the hypervisor virtual register so that the
> moment the guest unmasks the IRQ, an exception is raised. The only way
> to set the hypervisor register for another CPU would be to have it
> take a world-switch round.
> 
> So, I think if we simply change either of these lines, we need to
> signal the other CPU.
> 
> Marc, can you confirm?

We definitely need to signal the CPU an IRQ is pending. The VGIC may
help us here, as we can access another CPU's VGIC List Registers (via
the processor-specific base address of the Virtual interface control).
That would save sending an IPI to the target CPU.

	M.
-- 
Jazz is not dead. It just smells funny...