[RFC PATCH 00/17] KVM: PPC: 64-bit Book3E support

[RFC PATCH 00/17] KVM: PPC: 64-bit Book3E support

[Mihai Caraman]

This patchset adds 64-bit Book3E PowerPC support to KVM. It is intended
as a request for comment for scratch register changes and for the support
limited to bolted TLB miss exception handlers.
This work was validated on Freescale's e5500 cores using P5020DS boards.

This patchset is based on Alex G. kvm-ppc-next branch. For a ready to use
git tree, please check here:

  git://github.com/mcaraman/kvm.git 64-bit-booke

Current limitations:

- 64-bit guests must be configured without KVM support. CPU_FTR_EMB_HV setup
  for 64-bit non-hv will be addressed soon in a different patchset.

Prerequisite patches, availabe on top of the git tree:

- commit 7cd1afad10d981cbf4a0c8738bf7f5c0add0e50f:
	Make hard_irq_disable() actually hard-disable interrupts

- commit 9a5a0b80cf7e09bd6fadf1a66f27579d0f6d2795, required to run 32-bit
  guests on e5500 cores:
	powerpc/e5500: Set r5 to point to cpu spec in setup_cpu_e5500()

- commit 6c04342ba5ad7723d8b07d2ad4800607c0985c35, required to run 64-bit
  SMP guests:
	KVM: PPC: bookehv64: Add support for std/ld emulation

This patchset requires a qemu with e5500 support. For a ready to use git tree,
please check here:

  git://repo.or.cz/qemu/agraf.git ppc-e5500

To use qemu run:

  $ qemu-system-ppc64 -M mpc8544ds -cpu e5500 -nographic -kernel uImage \
    -machine dt_compatible=fsl,,P5020DS

Mike

Mihai Caraman (17):
  KVM: PPC64: booke: Set interrupt computation mode for 64-bit host
  KVM: PPC64: booke: Add EPCR support in mtspr/mfspr emulation
  KVM: PPC64: booke: Add EPCR support in sregs
  KVM: PPC64: booke: Add guest computation mode for irq delivery
  KVM: PPC: booke: Extend MAS2 EPN mask for 64-bit
  KVM: PPC: e500: Add emulation helper for getting instruction ea
  KVM: PPC: e500: Mask ea's high 32-bits in 32/64 instr emulation
  KVM: PPC: e500mc: Fix tlbilx emulation for 64-bit guests
  KVM: PPC64: booke: Hard disable interrupts when entering guest
  PowerPC: booke64: Refactor exception prolog for save/restore regs
  PowerPC: booke64: Fix machine check handler to use the right prolog
  PowerPC: booke64: Add DO_KVM kernel hooks
  PowerPC: booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int
  KVM: PPC32: bookehv: Remove GET_VCPU macro from exception handler
  KVM: PPC64: bookehv: Add support for interrupt handling
  KVM: PPC: e500: Silence bogus GCC warning in tlb code
  KVM: PPC: booke: Fix get_tb() compile error on 64-bit

 arch/powerpc/include/asm/exception-64e.h    |   14 ++--
 arch/powerpc/include/asm/kvm_booke_hv_asm.h |   12 +++-
 arch/powerpc/include/asm/mmu-book3e.h       |    2 +-
 arch/powerpc/include/asm/reg.h              |    6 +-
 arch/powerpc/kernel/exceptions-64e.S        |  127 ++++++++++++++++++---------
 arch/powerpc/kvm/booke.c                    |   49 +++++++++--
 arch/powerpc/kvm/booke.h                    |    6 ++
 arch/powerpc/kvm/booke_emulate.c            |   13 +++-
 arch/powerpc/kvm/bookehv_interrupts.S       |  127 ++++++++++++++++++++++++---
 arch/powerpc/kvm/e500.h                     |    8 +-
 arch/powerpc/kvm/e500_emulate.c             |   26 +++++-
 arch/powerpc/kvm/e500_tlb.c                 |   28 ++----
 arch/powerpc/kvm/e500mc.c                   |    8 ++-
 arch/powerpc/mm/tlb_low_64e.S               |   42 +++++----
 14 files changed, 347 insertions(+), 121 deletions(-)

-- 
1.7.4.1

[RFC PATCH 01/17] KVM: PPC64: booke: Set interrupt computation mode for 64-bit host

[Mihai Caraman]

64-bit host needs to remain in 64-bit mode when an exception take place.
Set interrupt computaion mode in EPCR register.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kvm/e500mc.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index fe6c1de..db97ee3 100644
--- a/arch/powerpc/kvm/e500mc.c
+++ b/arch/powerpc/kvm/e500mc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2010,2012 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Author: Varun Sethi, <varun.sethi@freescale.com>
  *
@@ -183,6 +183,9 @@ int kvmppc_core_vcpu_setup(struct kvm_vcpu *vcpu)
 
 	vcpu->arch.shadow_epcr = SPRN_EPCR_DSIGS | SPRN_EPCR_DGTMI | \
 				 SPRN_EPCR_DUVD;
+#ifdef CONFIG_64BIT
+	vcpu->arch.shadow_epcr |= SPRN_EPCR_ICM;
+#endif
 	vcpu->arch.shadow_msrp = MSRP_UCLEP | MSRP_DEP | MSRP_PMMP;
 	vcpu->arch.eplc = EPC_EGS | (vcpu->kvm->arch.lpid << EPC_ELPID_SHIFT);
 	vcpu->arch.epsc = vcpu->arch.eplc;
-- 
1.7.4.1

[RFC PATCH 02/17] KVM: PPC64: booke: Add EPCR support in mtspr/mfspr emulation

[Mihai Caraman]

Add EPCR support in booke mtspr/mfspr emulation. EPCR register is defined
only for 64-bit and HV categories, so it shoud be available only on 64-bit
virtual processors. Undefine the support for 32-bit builds.
Define a reusable setter function for vcpu's EPCR.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kvm/booke.c         |   12 +++++++++++-
 arch/powerpc/kvm/booke.h         |    6 ++++++
 arch/powerpc/kvm/booke_emulate.c |   13 ++++++++++++-
 3 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 72f13f4..f9fa260 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -13,7 +13,7 @@
  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  *
  * Copyright IBM Corp. 2007
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
  *
  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
  *          Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
@@ -1243,6 +1243,16 @@ void kvmppc_core_commit_memory_region(struct kvm *kvm,
 {
 }
 
+#ifdef CONFIG_64BIT
+void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr)
+{
+	vcpu->arch.epcr = new_epcr;
+	vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM;
+	if (vcpu->arch.epcr  & SPRN_EPCR_ICM)
+		vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM;
+}
+#endif
+
 void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr)
 {
 	vcpu->arch.tcr = new_tcr;
diff --git a/arch/powerpc/kvm/booke.h b/arch/powerpc/kvm/booke.h
index ba61974..e05b48f 100644
--- a/arch/powerpc/kvm/booke.h
+++ b/arch/powerpc/kvm/booke.h
@@ -69,6 +69,12 @@ extern unsigned long kvmppc_booke_handlers;
 void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr);
 void kvmppc_mmu_msr_notify(struct kvm_vcpu *vcpu, u32 old_msr);
 
+#ifdef CONFIG_64BIT
+void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr);
+#else
+static inline void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr) {}
+#endif
+
 void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr);
 void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits);
 void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits);
diff --git a/arch/powerpc/kvm/booke_emulate.c b/arch/powerpc/kvm/booke_emulate.c
index 6c76397..9cf2b95f 100644
--- a/arch/powerpc/kvm/booke_emulate.c
+++ b/arch/powerpc/kvm/booke_emulate.c
@@ -13,7 +13,7 @@
  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  *
  * Copyright IBM Corp. 2008
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
  *
  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
  */
@@ -207,6 +207,12 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
 	case SPRN_IVOR15:
 		vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
 		break;
+#ifdef CONFIG_64BIT
+	case SPRN_EPCR:
+		kvmppc_set_epcr(vcpu, spr_val);
+		mtspr(SPRN_EPCR, vcpu->arch.shadow_epcr);
+		break;
+#endif
 
 	default:
 		emulated = EMULATE_FAIL;
@@ -293,6 +299,11 @@ int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
 	case SPRN_IVOR15:
 		*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
 		break;
+#ifdef CONFIG_64BIT
+	case SPRN_EPCR:
+		*spr_val = vcpu->arch.epcr;
+		break;
+#endif
 
 	default:
 		emulated = EMULATE_FAIL;
-- 
1.7.4.1

[RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in sregs

[Mihai Caraman]

Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
for 64-bit hosts.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kvm/booke.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index f9fa260..d15c4b5 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -1052,6 +1052,9 @@ static void get_sregs_base(struct kvm_vcpu *vcpu,
 	u64 tb = get_tb();
 
 	sregs->u.e.features |= KVM_SREGS_E_BASE;
+#ifdef CONFIG_64BIT
+	sregs->u.e.features |= KVM_SREGS_E_64;
+#endif
 
 	sregs->u.e.csrr0 = vcpu->arch.csrr0;
 	sregs->u.e.csrr1 = vcpu->arch.csrr1;
@@ -1063,6 +1066,9 @@ static void get_sregs_base(struct kvm_vcpu *vcpu,
 	sregs->u.e.dec = kvmppc_get_dec(vcpu, tb);
 	sregs->u.e.tb = tb;
 	sregs->u.e.vrsave = vcpu->arch.vrsave;
+#ifdef CONFIG_64BIT
+	sregs->u.e.epcr = vcpu->arch.epcr;
+#endif
 }
 
 static int set_sregs_base(struct kvm_vcpu *vcpu,
@@ -1071,6 +1077,11 @@ static int set_sregs_base(struct kvm_vcpu *vcpu,
 	if (!(sregs->u.e.features & KVM_SREGS_E_BASE))
 		return 0;
 
+#ifdef CONFIG_64BIT
+	if (!(sregs->u.e.features & KVM_SREGS_E_64))
+		return 0;
+#endif
+
 	vcpu->arch.csrr0 = sregs->u.e.csrr0;
 	vcpu->arch.csrr1 = sregs->u.e.csrr1;
 	vcpu->arch.mcsr = sregs->u.e.mcsr;
@@ -1078,6 +1089,9 @@ static int set_sregs_base(struct kvm_vcpu *vcpu,
 	set_guest_dear(vcpu, sregs->u.e.dear);
 	vcpu->arch.vrsave = sregs->u.e.vrsave;
 	kvmppc_set_tcr(vcpu, sregs->u.e.tcr);
+#ifdef CONFIG_64BIT
+	kvmppc_set_epcr(vcpu, sregs->u.e.epcr);
+#endif
 
 	if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) {
 		vcpu->arch.dec = sregs->u.e.dec;
-- 
1.7.4.1

[RFC PATCH 04/17] KVM: PPC64: booke: Add guest computation mode for irq delivery

[Mihai Caraman]

When delivering guest IRQs, update MSR computaion mode according to guest
interrupt computation mode found in EPCR.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kvm/booke.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index d15c4b5..93b48e0 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -287,6 +287,7 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
 	bool crit;
 	bool keep_irq = false;
 	enum int_class int_class;
+	ulong msr_cm = 0;
 
 	/* Truncate crit indicators in 32 bit mode */
 	if (!(vcpu->arch.shared->msr & MSR_SF)) {
@@ -299,6 +300,10 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
 	/* ... and we're in supervisor mode */
 	crit = crit && !(vcpu->arch.shared->msr & MSR_PR);
 
+#ifdef CONFIG_64BIT
+	msr_cm = vcpu->arch.epcr & SPRN_EPCR_ICM ? MSR_CM : 0;
+#endif
+
 	if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) {
 		priority = BOOKE_IRQPRIO_EXTERNAL;
 		keep_irq = true;
@@ -381,7 +386,8 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
 			set_guest_esr(vcpu, vcpu->arch.queued_esr);
 		if (update_dear == true)
 			set_guest_dear(vcpu, vcpu->arch.queued_dear);
-		kvmppc_set_msr(vcpu, vcpu->arch.shared->msr & msr_mask);
+		kvmppc_set_msr(vcpu, (vcpu->arch.shared->msr & msr_mask)
+				| msr_cm);
 
 		if (!keep_irq)
 			clear_bit(priority, &vcpu->arch.pending_exceptions);
-- 
1.7.4.1

[RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2 EPN mask for 64-bit

[Mihai Caraman]

Extend MAS2 EPN mask for 64-bit hosts, to retain most significant bits.
Change get tlb eaddr to use this mask.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/include/asm/mmu-book3e.h |    2 +-
 arch/powerpc/kvm/e500.h               |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index eeabcdb..99d43e0 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -59,7 +59,7 @@
 #define MAS1_TSIZE_SHIFT	7
 #define MAS1_TSIZE(x)		(((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK)
 
-#define MAS2_EPN		0xFFFFF000
+#define MAS2_EPN		(~0xFFFUL)
 #define MAS2_X0			0x00000040
 #define MAS2_X1			0x00000020
 #define MAS2_W			0x00000010
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index aa8b814..3e31098 100644
--- a/arch/powerpc/kvm/e500.h
+++ b/arch/powerpc/kvm/e500.h
@@ -155,7 +155,7 @@ get_tlb_size(const struct kvm_book3e_206_tlb_entry *tlbe)
 
 static inline gva_t get_tlb_eaddr(const struct kvm_book3e_206_tlb_entry *tlbe)
 {
-	return tlbe->mas2 & 0xfffff000;
+	return tlbe->mas2 & MAS2_EPN;
 }
 
 static inline u64 get_tlb_bytes(const struct kvm_book3e_206_tlb_entry *tlbe)
-- 
1.7.4.1

[RFC PATCH 06/17] KVM: PPC: e500: Add emulation helper for getting instruction ea

[Mihai Caraman]

Add emulation helper for getting instruction ea and refactor tlb instruction
emulation to use it.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kvm/e500.h         |    6 +++---
 arch/powerpc/kvm/e500_emulate.c |   21 ++++++++++++++++++---
 arch/powerpc/kvm/e500_tlb.c     |   23 ++++++-----------------
 3 files changed, 27 insertions(+), 23 deletions(-)

diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index 3e31098..70bfed4 100644
--- a/arch/powerpc/kvm/e500.h
+++ b/arch/powerpc/kvm/e500.h
@@ -130,9 +130,9 @@ int kvmppc_e500_emul_mt_mmucsr0(struct kvmppc_vcpu_e500 *vcpu_e500,
 				ulong value);
 int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu);
 int kvmppc_e500_emul_tlbre(struct kvm_vcpu *vcpu);
-int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, int ra, int rb);
-int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, int ra, int rb);
-int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, int rb);
+int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, gva_t ea);
+int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, gva_t ea);
+int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, gva_t ea);
 int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 *vcpu_e500);
 void kvmppc_e500_tlb_uninit(struct kvmppc_vcpu_e500 *vcpu_e500);
 
diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
index 8b99e07..81288f7 100644
--- a/arch/powerpc/kvm/e500_emulate.c
+++ b/arch/powerpc/kvm/e500_emulate.c
@@ -82,6 +82,17 @@ static int kvmppc_e500_emul_msgsnd(struct kvm_vcpu *vcpu, int rb)
 }
 #endif
 
+static inline ulong kvmppc_get_ea_indexed(struct kvm_vcpu *vcpu, int ra, int rb)
+{
+	ulong ea;
+
+	ea = kvmppc_get_gpr(vcpu, rb);
+	if (ra)
+		ea += kvmppc_get_gpr(vcpu, ra);
+
+	return ea;
+}
+
 int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
                            unsigned int inst, int *advance)
 {
@@ -89,6 +100,7 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
 	int ra = get_ra(inst);
 	int rb = get_rb(inst);
 	int rt = get_rt(inst);
+	gva_t ea;
 
 	switch (get_op(inst)) {
 	case 31:
@@ -113,15 +125,18 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
 			break;
 
 		case XOP_TLBSX:
-			emulated = kvmppc_e500_emul_tlbsx(vcpu,rb);
+			ea = kvmppc_get_ea_indexed(vcpu, ra, rb);
+			emulated = kvmppc_e500_emul_tlbsx(vcpu, ea);
 			break;
 
 		case XOP_TLBILX:
-			emulated = kvmppc_e500_emul_tlbilx(vcpu, rt, ra, rb);
+			ea = kvmppc_get_ea_indexed(vcpu, ra, rb);
+			emulated = kvmppc_e500_emul_tlbilx(vcpu, rt, ea);
 			break;
 
 		case XOP_TLBIVAX:
-			emulated = kvmppc_e500_emul_tlbivax(vcpu, ra, rb);
+			ea = kvmppc_get_ea_indexed(vcpu, ra, rb);
+			emulated = kvmppc_e500_emul_tlbivax(vcpu, ea);
 			break;
 
 		default:
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
index c510fc9..2175a58 100644
--- a/arch/powerpc/kvm/e500_tlb.c
+++ b/arch/powerpc/kvm/e500_tlb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Author: Yu Liu, yu.liu@freescale.com
  *         Scott Wood, scottwood@freescale.com
@@ -680,14 +680,11 @@ int kvmppc_e500_emul_mt_mmucsr0(struct kvmppc_vcpu_e500 *vcpu_e500, ulong value)
 	return EMULATE_DONE;
 }
 
-int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, int ra, int rb)
+int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, gva_t ea)
 {
 	struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
 	unsigned int ia;
 	int esel, tlbsel;
-	gva_t ea;
-
-	ea = ((ra) ? kvmppc_get_gpr(vcpu, ra) : 0) + kvmppc_get_gpr(vcpu, rb);
 
 	ia = (ea >> 2) & 0x1;
 
@@ -731,14 +728,9 @@ static void tlbilx_all(struct kvmppc_vcpu_e500 *vcpu_e500, int tlbsel,
 }
 
 static void tlbilx_one(struct kvmppc_vcpu_e500 *vcpu_e500, int pid,
-		       int ra, int rb)
+		       gva_t ea)
 {
 	int tlbsel, esel;
-	gva_t ea;
-
-	ea = kvmppc_get_gpr(&vcpu_e500->vcpu, rb);
-	if (ra)
-		ea += kvmppc_get_gpr(&vcpu_e500->vcpu, ra);
 
 	for (tlbsel = 0; tlbsel < 2; tlbsel++) {
 		esel = kvmppc_e500_tlb_index(vcpu_e500, ea, tlbsel, pid, -1);
@@ -750,7 +742,7 @@ static void tlbilx_one(struct kvmppc_vcpu_e500 *vcpu_e500, int pid,
 	}
 }
 
-int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, int ra, int rb)
+int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, gva_t ea)
 {
 	struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
 	int pid = get_cur_spid(vcpu);
@@ -759,7 +751,7 @@ int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, int ra, int rb)
 		tlbilx_all(vcpu_e500, 0, pid, rt);
 		tlbilx_all(vcpu_e500, 1, pid, rt);
 	} else if (rt == 3) {
-		tlbilx_one(vcpu_e500, pid, ra, rb);
+		tlbilx_one(vcpu_e500, pid, ea);
 	}
 
 	return EMULATE_DONE;
@@ -784,16 +776,13 @@ int kvmppc_e500_emul_tlbre(struct kvm_vcpu *vcpu)
 	return EMULATE_DONE;
 }
 
-int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, int rb)
+int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, gva_t ea)
 {
 	struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
 	int as = !!get_cur_sas(vcpu);
 	unsigned int pid = get_cur_spid(vcpu);
 	int esel, tlbsel;
 	struct kvm_book3e_206_tlb_entry *gtlbe = NULL;
-	gva_t ea;
-
-	ea = kvmppc_get_gpr(vcpu, rb);
 
 	for (tlbsel = 0; tlbsel < 2; tlbsel++) {
 		esel = kvmppc_e500_tlb_index(vcpu_e500, ea, tlbsel, pid, as);
-- 
1.7.4.1

[RFC PATCH 07/17] KVM: PPC: e500: Mask ea's high 32-bits in 32/64 instr emulation

[Mihai Caraman]

Mask high 32 bits of effective address in emulation layer, for guests running
in 32-bit mode.
MAS2's high-order 32 bits represents the upper 32 bits of the effective address
of the page. Mask it too for tlbwe instruction emulation.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kvm/e500_emulate.c |    5 ++++-
 arch/powerpc/kvm/e500_tlb.c     |    2 ++
 2 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
index 81288f7..94305db 100644
--- a/arch/powerpc/kvm/e500_emulate.c
+++ b/arch/powerpc/kvm/e500_emulate.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Author: Yu Liu, <yu.liu@freescale.com>
  *
@@ -90,6 +90,9 @@ static inline ulong kvmppc_get_ea_indexed(struct kvm_vcpu *vcpu, int ra, int rb)
 	if (ra)
 		ea += kvmppc_get_gpr(vcpu, ra);
 
+	if (!(vcpu->arch.shared->msr & MSR_CM))
+		ea &= 0xffffffffUL;
+
 	return ea;
 }
 
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
index 2175a58..3ed4e7d 100644
--- a/arch/powerpc/kvm/e500_tlb.c
+++ b/arch/powerpc/kvm/e500_tlb.c
@@ -862,6 +862,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
 
 	gtlbe->mas1 = vcpu->arch.shared->mas1;
 	gtlbe->mas2 = vcpu->arch.shared->mas2;
+	if (!(vcpu->arch.shared->msr & MSR_CM))
+		gtlbe->mas2 &= 0xffffffffUL;
 	gtlbe->mas7_3 = vcpu->arch.shared->mas7_3;
 
 	trace_kvm_booke206_gtlb_write(vcpu->arch.shared->mas0, gtlbe->mas1,
-- 
1.7.4.1

[RFC PATCH 08/17] KVM: PPC: e500mc: Fix tlbilx emulation for 64-bit guests

[Mihai Caraman]

tlbilxva emulation was using an u32 variable for guest effective address.
Replace it with gva_t type to handle 64-bit guests.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kvm/e500mc.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index db97ee3..1f89d26 100644
--- a/arch/powerpc/kvm/e500mc.c
+++ b/arch/powerpc/kvm/e500mc.c
@@ -57,7 +57,8 @@ void kvmppc_e500_tlbil_one(struct kvmppc_vcpu_e500 *vcpu_e500,
 			   struct kvm_book3e_206_tlb_entry *gtlbe)
 {
 	unsigned int tid, ts;
-	u32 val, eaddr, lpid;
+	gva_t eaddr;
+	u32 val, lpid;
 	unsigned long flags;
 
 	ts = get_tlb_ts(gtlbe);
-- 
1.7.4.1

[RFC PATCH 09/17] KVM: PPC64: booke: Hard disable interrupts when entering guest

[Mihai Caraman]

64-bit host runs with lazy interrupt disabling, so local_irq_disable() does
not disable interrupts right away and does not protect against preemption
required by __kvmppc_vcpu_run(). Define a macro for 64-bit to use
hard_irq_disable().

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kvm/booke.c |   14 ++++++++++----
 1 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 93b48e0..db05692 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -45,6 +45,12 @@ unsigned long kvmppc_booke_handlers;
 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
 
+#ifdef CONFIG_64BIT
+#define _hard_irq_disable() hard_irq_disable()
+#else
+#define _hard_irq_disable() local_irq_disable()
+#endif
+
 struct kvm_stats_debugfs_item debugfs_entries[] = {
 	{ "mmio",       VCPU_STAT(mmio_exits) },
 	{ "dcr",        VCPU_STAT(dcr_exits) },
@@ -456,7 +462,7 @@ int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu)
 		local_irq_enable();
 		kvm_vcpu_block(vcpu);
 		clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
-		local_irq_disable();
+		_hard_irq_disable();
 
 		kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS);
 		r = 1;
@@ -480,7 +486,7 @@ static int kvmppc_prepare_to_enter(struct kvm_vcpu *vcpu)
 		if (need_resched()) {
 			local_irq_enable();
 			cond_resched();
-			local_irq_disable();
+			_hard_irq_disable();
 			continue;
 		}
 
@@ -515,7 +521,7 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 		return -EINVAL;
 	}
 
-	local_irq_disable();
+	_hard_irq_disable();
 	if (kvmppc_prepare_to_enter(vcpu)) {
 		kvm_run->exit_reason = KVM_EXIT_INTR;
 		ret = -EINTR;
@@ -955,7 +961,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
 	 * aren't already exiting to userspace for some other reason.
 	 */
 	if (!(r & RESUME_HOST)) {
-		local_irq_disable();
+		_hard_irq_disable();
 		if (kvmppc_prepare_to_enter(vcpu)) {
 			run->exit_reason = KVM_EXIT_INTR;
 			r = (-EINTR << 2) | RESUME_HOST | (r & RESUME_FLAG_NV);
-- 
1.7.4.1

[RFC PATCH 10/17] PowerPC: booke64: Refactor exception prolog for save/restore regs

[Mihai Caraman]

Refactor exception prolog to allow save/restore register parameters. Add
addition none definition for exception prolog usage.
This is needed for exceptions like Guest Doorbell that use GSRRx regsiters
which do not map on exception type.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kernel/exceptions-64e.S |   23 ++++++++---------------
 1 files changed, 8 insertions(+), 15 deletions(-)

diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 7215cc2..52aa96b 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -35,7 +35,7 @@
 #define	SPECIAL_EXC_FRAME_SIZE	INT_FRAME_SIZE
 
 /* Exception prolog code for all exceptions */
-#define EXCEPTION_PROLOG(n, type, addition)				    \
+#define EXCEPTION_PROLOG(n, type, srr0, srr1, addition)		     	    \
 	mtspr	SPRN_SPRG_##type##_SCRATCH,r13;	/* get spare registers */   \
 	mfspr	r13,SPRN_SPRG_PACA;	/* get PACA */			    \
 	std	r10,PACA_EX##type+EX_R10(r13);				    \
@@ -44,54 +44,47 @@
 	addition;			/* additional code for that exc. */ \
 	std	r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
 	stw	r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
-	mfspr	r11,SPRN_##type##_SRR1;/* what are we coming from */	    \
+	mfspr	r11,srr1;/* what are we coming from */	    		    \
 	type##_SET_KSTACK;		/* get special stack if necessary */\
 	andi.	r10,r11,MSR_PR;		/* save stack pointer */	    \
 	beq	1f;			/* branch around if supervisor */   \
 	ld	r1,PACAKSAVE(r13);	/* get kernel stack coming from usr */\
 1:	cmpdi	cr1,r1,0;		/* check if SP makes sense */	    \
 	bge-	cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
-	mfspr	r10,SPRN_##type##_SRR0;	/* read SRR0 before touching stack */
+	mfspr	r10,srr0;		/* read SRR0 before touching stack */
 
 /* Exception type-specific macros */
 #define	GEN_SET_KSTACK							    \
 	subi	r1,r1,INT_FRAME_SIZE;	/* alloc frame on kernel stack */
-#define SPRN_GEN_SRR0	SPRN_SRR0
-#define SPRN_GEN_SRR1	SPRN_SRR1
 
 #define CRIT_SET_KSTACK						            \
 	ld	r1,PACA_CRIT_STACK(r13);				    \
 	subi	r1,r1,SPECIAL_EXC_FRAME_SIZE;
-#define SPRN_CRIT_SRR0	SPRN_CSRR0
-#define SPRN_CRIT_SRR1	SPRN_CSRR1
 
 #define DBG_SET_KSTACK						            \
 	ld	r1,PACA_DBG_STACK(r13);					    \
 	subi	r1,r1,SPECIAL_EXC_FRAME_SIZE;
-#define SPRN_DBG_SRR0	SPRN_DSRR0
-#define SPRN_DBG_SRR1	SPRN_DSRR1
 
 #define MC_SET_KSTACK						            \
 	ld	r1,PACA_MC_STACK(r13);					    \
 	subi	r1,r1,SPECIAL_EXC_FRAME_SIZE;
-#define SPRN_MC_SRR0	SPRN_MCSRR0
-#define SPRN_MC_SRR1	SPRN_MCSRR1
 
 #define NORMAL_EXCEPTION_PROLOG(n, addition)				    \
-	EXCEPTION_PROLOG(n, GEN, addition##_GEN(n))
+	EXCEPTION_PROLOG(n, GEN, SPRN_SRR0, SPRN_SRR1, addition##_GEN(n))
 
 #define CRIT_EXCEPTION_PROLOG(n, addition)				    \
-	EXCEPTION_PROLOG(n, CRIT, addition##_CRIT(n))
+	EXCEPTION_PROLOG(n, CRIT, SPRN_CSRR0, SPRN_CSRR1, addition##_CRIT(n))
 
 #define DBG_EXCEPTION_PROLOG(n, addition)				    \
-	EXCEPTION_PROLOG(n, DBG, addition##_DBG(n))
+	EXCEPTION_PROLOG(n, DBG, SPRN_DSRR0, SPRN_DSRR1, addition##_DBG(n))
 
 #define MC_EXCEPTION_PROLOG(n, addition)				    \
-	EXCEPTION_PROLOG(n, MC, addition##_MC(n))
+	EXCEPTION_PROLOG(n, MC, SPRN_MCSRR0, SPRN_MCSRR1, addition##_MC(n))
 
 
 /* Variants of the "addition" argument for the prolog
  */
+#define PROLOG_ADDITION_NONE
 #define PROLOG_ADDITION_NONE_GEN(n)
 #define PROLOG_ADDITION_NONE_CRIT(n)
 #define PROLOG_ADDITION_NONE_DBG(n)
-- 
1.7.4.1

[RFC PATCH 11/17] PowerPC: booke64: Fix machine check handler to use the right prolog

[Mihai Caraman]

Machine check exception handler was using a wrong prolog. Hypervisors, like
KVM, which are called early from the exception handler rely on the interrupt
source.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kernel/exceptions-64e.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 52aa96b..06f7aec 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -290,7 +290,7 @@ interrupt_end_book3e:
 
 /* Machine Check Interrupt */
 	START_EXCEPTION(machine_check);
-	CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
+	MC_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
 //	EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE)
 //	bl	special_reg_save_mc
 //	addi	r3,r1,STACK_FRAME_OVERHEAD
-- 
1.7.4.1

[RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Mihai Caraman]

Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit booke
see head_fsl_booke.S file. Extend interrupt handlers' parameter list with
interrupt vector numbers to accomodate the macro. Rework Guest Doorbell
handler to use the proper GSRRx save/restore registers.
Only the bolted version of tlb miss handers is addressed now.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kernel/exceptions-64e.S |  114 ++++++++++++++++++++++++----------
 arch/powerpc/mm/tlb_low_64e.S        |   14 +++-
 2 files changed, 92 insertions(+), 36 deletions(-)

diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 06f7aec..a60f81f 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -25,6 +25,8 @@
 #include <asm/ppc-opcode.h>
 #include <asm/mmu.h>
 #include <asm/hw_irq.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_booke_hv_asm.h>
 
 /* XXX This will ultimately add space for a special exception save
  *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
@@ -34,13 +36,24 @@
  */
 #define	SPECIAL_EXC_FRAME_SIZE	INT_FRAME_SIZE
 
+#ifdef CONFIG_KVM_BOOKE_HV
+#define KVM_BOOKE_HV_MFSPR(reg, spr)				\
+	BEGIN_FTR_SECTION					\
+		mfspr	reg, spr;			  	\
+	END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
+#else
+#define KVM_BOOKE_HV_MFSPR(reg, spr)
+#endif
+
 /* Exception prolog code for all exceptions */
-#define EXCEPTION_PROLOG(n, type, srr0, srr1, addition)		     	    \
+#define EXCEPTION_PROLOG(n, intnum, type, srr0, srr1, addition)		    \
 	mtspr	SPRN_SPRG_##type##_SCRATCH,r13;	/* get spare registers */   \
 	mfspr	r13,SPRN_SPRG_PACA;	/* get PACA */			    \
 	std	r10,PACA_EX##type+EX_R10(r13);				    \
 	std	r11,PACA_EX##type+EX_R11(r13);				    \
 	mfcr	r10;			/* save CR */			    \
+	KVM_BOOKE_HV_MFSPR(r11,srr1);			    		    \
+	DO_KVM	intnum,srr1;				    		    \
 	addition;			/* additional code for that exc. */ \
 	std	r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
 	stw	r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
@@ -69,17 +82,21 @@
 	ld	r1,PACA_MC_STACK(r13);					    \
 	subi	r1,r1,SPECIAL_EXC_FRAME_SIZE;
 
-#define NORMAL_EXCEPTION_PROLOG(n, addition)				    \
-	EXCEPTION_PROLOG(n, GEN, SPRN_SRR0, SPRN_SRR1, addition##_GEN(n))
+#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition)			    \
+	EXCEPTION_PROLOG(n, intnum, GEN, SPRN_SRR0, SPRN_SRR1,		    \
+					 addition##_GEN(n))
 
-#define CRIT_EXCEPTION_PROLOG(n, addition)				    \
-	EXCEPTION_PROLOG(n, CRIT, SPRN_CSRR0, SPRN_CSRR1, addition##_CRIT(n))
+#define CRIT_EXCEPTION_PROLOG(n, intnum, addition)			    \
+	EXCEPTION_PROLOG(n, intnum, CRIT, SPRN_CSRR0, SPRN_CSRR1, 	    \
+					 addition##_CRIT(n))
 
-#define DBG_EXCEPTION_PROLOG(n, addition)				    \
-	EXCEPTION_PROLOG(n, DBG, SPRN_DSRR0, SPRN_DSRR1, addition##_DBG(n))
+#define DBG_EXCEPTION_PROLOG(n, intnum, addition)			    \
+	EXCEPTION_PROLOG(n, intnum, DBG, SPRN_DSRR0, SPRN_DSRR1, 	    \
+					 addition##_DBG(n))
 
-#define MC_EXCEPTION_PROLOG(n, addition)				    \
-	EXCEPTION_PROLOG(n, MC, SPRN_MCSRR0, SPRN_MCSRR1, addition##_MC(n))
+#define MC_EXCEPTION_PROLOG(n, intnum, addition)			    \
+	EXCEPTION_PROLOG(n, intnum, MC, SPRN_MCSRR0, SPRN_MCSRR1, 	    \
+					 addition##_MC(n))
 
 
 /* Variants of the "addition" argument for the prolog
@@ -226,9 +243,9 @@ exc_##n##_bad_stack:							    \
 1:
 
 
-#define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack)			\
+#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack)		\
 	START_EXCEPTION(label);						\
-	NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE)	\
+	NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
 	EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE)		\
 	ack(r8);							\
 	CHECK_NAPPING();						\
@@ -279,7 +296,8 @@ interrupt_end_book3e:
 
 /* Critical Input Interrupt */
 	START_EXCEPTION(critical_input);
-	CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
+	CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
+			      PROLOG_ADDITION_NONE)
 //	EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE)
 //	bl	special_reg_save_crit
 //	CHECK_NAPPING();
@@ -290,7 +308,8 @@ interrupt_end_book3e:
 
 /* Machine Check Interrupt */
 	START_EXCEPTION(machine_check);
-	MC_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
+	MC_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_MACHINE_CHECK,
+			    PROLOG_ADDITION_NONE)
 //	EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE)
 //	bl	special_reg_save_mc
 //	addi	r3,r1,STACK_FRAME_OVERHEAD
@@ -301,7 +320,8 @@ interrupt_end_book3e:
 
 /* Data Storage Interrupt */
 	START_EXCEPTION(data_storage)
-	NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
+	NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
+				PROLOG_ADDITION_2REGS)
 	mfspr	r14,SPRN_DEAR
 	mfspr	r15,SPRN_ESR
 	EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE)
@@ -309,18 +329,21 @@ interrupt_end_book3e:
 
 /* Instruction Storage Interrupt */
 	START_EXCEPTION(instruction_storage);
-	NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
+	NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
+				PROLOG_ADDITION_2REGS)
 	li	r15,0
 	mr	r14,r10
 	EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE)
 	b	storage_fault_common
 
 /* External Input Interrupt */
-	MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE)
+	MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
+			   external_input, .do_IRQ, ACK_NONE)
 
 /* Alignment */
 	START_EXCEPTION(alignment);
-	NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS)
+	NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
+				PROLOG_ADDITION_2REGS)
 	mfspr	r14,SPRN_DEAR
 	mfspr	r15,SPRN_ESR
 	EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
@@ -328,7 +351,8 @@ interrupt_end_book3e:
 
 /* Program Interrupt */
 	START_EXCEPTION(program);
-	NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
+	NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
+				PROLOG_ADDITION_1REG)
 	mfspr	r14,SPRN_ESR
 	EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE)
 	std	r14,_DSISR(r1)
@@ -340,7 +364,8 @@ interrupt_end_book3e:
 
 /* Floating Point Unavailable Interrupt */
 	START_EXCEPTION(fp_unavailable);
-	NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
+	NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
+				PROLOG_ADDITION_NONE)
 	/* we can probably do a shorter exception entry for that one... */
 	EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
 	ld	r12,_MSR(r1)
@@ -355,14 +380,17 @@ interrupt_end_book3e:
 	b	.ret_from_except
 
 /* Decrementer Interrupt */
-	MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
+	MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
+			   decrementer, .timer_interrupt, ACK_DEC)
 
 /* Fixed Interval Timer Interrupt */
-	MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT)
+	MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
+			   fixed_interval, .unknown_exception, ACK_FIT)
 
 /* Watchdog Timer Interrupt */
 	START_EXCEPTION(watchdog);
-	CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
+	CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
+			      PROLOG_ADDITION_NONE)
 //	EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE)
 //	bl	special_reg_save_crit
 //	CHECK_NAPPING();
@@ -381,7 +409,8 @@ interrupt_end_book3e:
 
 /* Auxiliary Processor Unavailable Interrupt */
 	START_EXCEPTION(ap_unavailable);
-	NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
+	NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
+				PROLOG_ADDITION_NONE)
 	EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE)
 	bl	.save_nvgprs
 	addi	r3,r1,STACK_FRAME_OVERHEAD
@@ -390,7 +419,8 @@ interrupt_end_book3e:
 
 /* Debug exception as a critical interrupt*/
 	START_EXCEPTION(debug_crit);
-	CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
+	CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
+			      PROLOG_ADDITION_2REGS)
 
 	/*
 	 * If there is a single step or branch-taken exception in an
@@ -455,7 +485,8 @@ kernel_dbg_exc:
 
 /* Debug exception as a debug interrupt*/
 	START_EXCEPTION(debug_debug);
-	DBG_EXCEPTION_PROLOG(0xd08, PROLOG_ADDITION_2REGS)
+	DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
+						 PROLOG_ADDITION_2REGS)
 
 	/*
 	 * If there is a single step or branch-taken exception in an
@@ -516,18 +547,21 @@ kernel_dbg_exc:
 	b	.ret_from_except
 
 	START_EXCEPTION(perfmon);
-	NORMAL_EXCEPTION_PROLOG(0x260, PROLOG_ADDITION_NONE)
+	NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
+				PROLOG_ADDITION_NONE)
 	EXCEPTION_COMMON(0x260, PACA_EXGEN, INTS_DISABLE)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	bl	.performance_monitor_exception
 	b	.ret_from_except_lite
 
 /* Doorbell interrupt */
-	MASKABLE_EXCEPTION(0x280, doorbell, .doorbell_exception, ACK_NONE)
+	MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
+			   doorbell, .doorbell_exception, ACK_NONE)
 
 /* Doorbell critical Interrupt */
 	START_EXCEPTION(doorbell_crit);
-	CRIT_EXCEPTION_PROLOG(0x2a0, PROLOG_ADDITION_NONE)
+	CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
+			      PROLOG_ADDITION_NONE)
 //	EXCEPTION_COMMON(0x2a0, PACA_EXCRIT, INTS_DISABLE)
 //	bl	special_reg_save_crit
 //	CHECK_NAPPING();
@@ -536,12 +570,24 @@ kernel_dbg_exc:
 //	b	ret_from_crit_except
 	b	.
 
-/* Guest Doorbell */
-	MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception, ACK_NONE)
+/*
+ *	Guest doorbell interrupt
+ *	This general exception use GSRRx save/restore registers
+ */
+	START_EXCEPTION(guest_doorbell);
+	EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, GEN,
+			 SPRN_GSRR0, SPRN_GSRR1, PROLOG_ADDITION_NONE)
+	EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	bl	.save_nvgprs
+	INTS_RESTORE_HARD
+	bl	.unknown_exception
+	b	.ret_from_except
 
 /* Guest Doorbell critical Interrupt */
 	START_EXCEPTION(guest_doorbell_crit);
-	CRIT_EXCEPTION_PROLOG(0x2e0, PROLOG_ADDITION_NONE)
+	CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
+			      PROLOG_ADDITION_NONE)
 //	EXCEPTION_COMMON(0x2e0, PACA_EXCRIT, INTS_DISABLE)
 //	bl	special_reg_save_crit
 //	CHECK_NAPPING();
@@ -552,7 +598,8 @@ kernel_dbg_exc:
 
 /* Hypervisor call */
 	START_EXCEPTION(hypercall);
-	NORMAL_EXCEPTION_PROLOG(0x310, PROLOG_ADDITION_NONE)
+	NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
+			        PROLOG_ADDITION_NONE)
 	EXCEPTION_COMMON(0x310, PACA_EXGEN, INTS_KEEP)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	bl	.save_nvgprs
@@ -562,7 +609,8 @@ kernel_dbg_exc:
 
 /* Embedded Hypervisor priviledged  */
 	START_EXCEPTION(ehpriv);
-	NORMAL_EXCEPTION_PROLOG(0x320, PROLOG_ADDITION_NONE)
+	NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
+			        PROLOG_ADDITION_NONE)
 	EXCEPTION_COMMON(0x320, PACA_EXGEN, INTS_KEEP)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	bl	.save_nvgprs
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index ff672bd..88feaaa 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -20,6 +20,8 @@
 #include <asm/pgtable.h>
 #include <asm/exception-64e.h>
 #include <asm/ppc-opcode.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_booke_hv_asm.h>
 
 #ifdef CONFIG_PPC_64K_PAGES
 #define VPTE_PMD_SHIFT	(PTE_INDEX_SIZE+1)
@@ -37,12 +39,18 @@
  *                                                                    *
  **********************************************************************/
 
-.macro tlb_prolog_bolted addr
+.macro tlb_prolog_bolted intnum addr
 	mtspr	SPRN_SPRG_TLB_SCRATCH,r13
 	mfspr	r13,SPRN_SPRG_PACA
 	std	r10,PACA_EXTLB+EX_TLB_R10(r13)
 	mfcr	r10
 	std	r11,PACA_EXTLB+EX_TLB_R11(r13)
+#ifdef CONFIG_KVM_BOOKE_HV
+BEGIN_FTR_SECTION
+	mfspr	r11, SPRN_SRR1
+END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
+#endif
+	DO_KVM	\intnum, SPRN_SRR1
 	std	r16,PACA_EXTLB+EX_TLB_R16(r13)
 	mfspr	r16,\addr		/* get faulting address */
 	std	r14,PACA_EXTLB+EX_TLB_R14(r13)
@@ -66,7 +74,7 @@
 
 /* Data TLB miss */
 	START_EXCEPTION(data_tlb_miss_bolted)
-	tlb_prolog_bolted SPRN_DEAR
+	tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
 
 	/* We need _PAGE_PRESENT and  _PAGE_ACCESSED set */
 
@@ -214,7 +222,7 @@ itlb_miss_fault_bolted:
 
 /* Instruction TLB miss */
 	START_EXCEPTION(instruction_tlb_miss_bolted)
-	tlb_prolog_bolted SPRN_SRR0
+	tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
 
 	rldicl.	r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
 	srdi	r15,r16,60		/* get region */
-- 
1.7.4.1

[RFC PATCH 13/17] PowerPC: booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int

[Mihai Caraman]

Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
SPRG4-7 registers will be clobbered.
For bolted TLB miss exception handlers, which is the version currently
supported by KVM, use SPRN_SPRG_GEN_SCRATCH (aka SPRG0) instead of
SPRN_SPRG_TLB_SCRATCH (aka SPRG6) and replace TLB with GEN PACA slots to
keep consitency.
For critical exception handler use SPRG3 instead of SPRG7.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/include/asm/exception-64e.h |   14 +++++++-------
 arch/powerpc/include/asm/reg.h           |    6 +++---
 arch/powerpc/mm/tlb_low_64e.S            |   28 ++++++++++++++--------------
 3 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h
index ac13add..c90a9a4 100644
--- a/arch/powerpc/include/asm/exception-64e.h
+++ b/arch/powerpc/include/asm/exception-64e.h
@@ -38,8 +38,11 @@
  */
 
 
-/* We are out of SPRGs so we save some things in the PACA. The normal
- * exception frame is smaller than the CRIT or MC one though
+/* We are out of SPRGs so we save some things in the 8 slots available in PACA.
+ * The normal exception frame is smaller than the CRIT or MC one though
+ *
+ * Bolted TLB miss exception variant also uses these slots which in combination
+ * with pgd and kernel_pgd fits in one 64-byte cache line.
  */
 #define EX_R1		(0 * 8)
 #define EX_CR		(1 * 8)
@@ -47,13 +50,10 @@
 #define EX_R11		(3 * 8)
 #define EX_R14		(4 * 8)
 #define EX_R15		(5 * 8)
+#define EX_R16		(6 * 8)
 
 /*
- * The TLB miss exception uses different slots.
- *
- * The bolted variant uses only the first six fields,
- * which in combination with pgd and kernel_pgd fits in
- * one 64-byte cache line.
+ * PACA slots offset for standard TLB miss exception.
  */
 
 #define EX_TLB_R10	( 0 * 8)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index f0cb7f4..51c14a7 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -760,10 +760,10 @@
  * 64-bit embedded
  *	- SPRG0 generic exception scratch
  *	- SPRG2 TLB exception stack
- *	- SPRG3 unused (user visible)
+ *	- SPRG3 critical exception scratch (user visible)
  *	- SPRG4 unused (user visible)
  *	- SPRG6 TLB miss scratch (user visible, sorry !)
- *	- SPRG7 critical exception scratch
+ *	- SPRG7 unused (user visible)
  *	- SPRG8 machine check exception scratch
  *	- SPRG9 debug exception scratch
  *
@@ -857,7 +857,7 @@
 
 #ifdef CONFIG_PPC_BOOK3E_64
 #define SPRN_SPRG_MC_SCRATCH	SPRN_SPRG8
-#define SPRN_SPRG_CRIT_SCRATCH	SPRN_SPRG7
+#define SPRN_SPRG_CRIT_SCRATCH	SPRN_SPRG3
 #define SPRN_SPRG_DBG_SCRATCH	SPRN_SPRG9
 #define SPRN_SPRG_TLB_EXFRAME	SPRN_SPRG2
 #define SPRN_SPRG_TLB_SCRATCH	SPRN_SPRG6
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index 88feaaa..4192ade 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -40,36 +40,36 @@
  **********************************************************************/
 
 .macro tlb_prolog_bolted intnum addr
-	mtspr	SPRN_SPRG_TLB_SCRATCH,r13
+	mtspr	SPRN_SPRG_GEN_SCRATCH,r13
 	mfspr	r13,SPRN_SPRG_PACA
-	std	r10,PACA_EXTLB+EX_TLB_R10(r13)
+	std	r10,PACA_EXGEN+EX_R10(r13)
 	mfcr	r10
-	std	r11,PACA_EXTLB+EX_TLB_R11(r13)
+	std	r11,PACA_EXGEN+EX_R11(r13)
 #ifdef CONFIG_KVM_BOOKE_HV
 BEGIN_FTR_SECTION
 	mfspr	r11, SPRN_SRR1
 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 #endif
 	DO_KVM	\intnum, SPRN_SRR1
-	std	r16,PACA_EXTLB+EX_TLB_R16(r13)
+	std	r16,PACA_EXGEN+EX_R16(r13)
 	mfspr	r16,\addr		/* get faulting address */
-	std	r14,PACA_EXTLB+EX_TLB_R14(r13)
+	std	r14,PACA_EXGEN+EX_R14(r13)
 	ld	r14,PACAPGD(r13)
-	std	r15,PACA_EXTLB+EX_TLB_R15(r13)
-	std	r10,PACA_EXTLB+EX_TLB_CR(r13)
+	std	r15,PACA_EXGEN+EX_R15(r13)
+	std	r10,PACA_EXGEN+EX_CR(r13)
 	TLB_MISS_PROLOG_STATS_BOLTED
 .endm
 
 .macro tlb_epilog_bolted
-	ld	r14,PACA_EXTLB+EX_TLB_CR(r13)
-	ld	r10,PACA_EXTLB+EX_TLB_R10(r13)
-	ld	r11,PACA_EXTLB+EX_TLB_R11(r13)
+	ld	r14,PACA_EXGEN+EX_CR(r13)
+	ld	r10,PACA_EXGEN+EX_R10(r13)
+	ld	r11,PACA_EXGEN+EX_R11(r13)
 	mtcr	r14
-	ld	r14,PACA_EXTLB+EX_TLB_R14(r13)
-	ld	r15,PACA_EXTLB+EX_TLB_R15(r13)
+	ld	r14,PACA_EXGEN+EX_R14(r13)
+	ld	r15,PACA_EXGEN+EX_R15(r13)
 	TLB_MISS_RESTORE_STATS_BOLTED
-	ld	r16,PACA_EXTLB+EX_TLB_R16(r13)
-	mfspr	r13,SPRN_SPRG_TLB_SCRATCH
+	ld	r16,PACA_EXGEN+EX_R16(r13)
+	mfspr	r13,SPRN_SPRG_GEN_SCRATCH
 .endm
 
 /* Data TLB miss */
-- 
1.7.4.1

[RFC PATCH 14/17] KVM: PPC32: bookehv: Remove GET_VCPU macro from exception handler

[Mihai Caraman]

GET_VCPU define will not be implemented for 64-bit for performance reasons
so get rid of it also on 32-bit.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kvm/bookehv_interrupts.S |    7 ++-----
 1 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S
index 6048a00..dff8ed4 100644
--- a/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/arch/powerpc/kvm/bookehv_interrupts.S
@@ -32,9 +32,6 @@
 
 #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
 
-#define GET_VCPU(vcpu, thread)	\
-	PPC_LL	vcpu, THREAD_KVM_VCPU(thread)
-
 #define LONGBYTES		(BITS_PER_LONG / 8)
 
 #define VCPU_GPR(n)     	(VCPU_GPRS + (n * LONGBYTES))
@@ -210,7 +207,7 @@
  */
 .macro kvm_handler intno srr0, srr1, flags
 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
-	GET_VCPU(r11, r10)
+	PPC_LL	r11, THREAD_KVM_VCPU(r10)
 	PPC_STL r3, VCPU_GPR(r3)(r11)
 	mfspr	r3, SPRN_SPRG_RSCRATCH0
 	PPC_STL	r4, VCPU_GPR(r4)(r11)
@@ -237,7 +234,7 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1)
 .macro kvm_lvl_handler intno scratch srr0, srr1, flags
 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
 	mfspr	r10, SPRN_SPRG_THREAD
-	GET_VCPU(r11, r10)
+	PPC_LL	r11, THREAD_KVM_VCPU(r10)
 	PPC_STL r3, VCPU_GPR(r3)(r11)
 	mfspr	r3, \scratch
 	PPC_STL	r4, VCPU_GPR(r4)(r11)
-- 
1.7.4.1

[RFC PATCH 15/17] KVM: PPC64: bookehv: Add support for interrupt handling

[Mihai Caraman]

Add bookehv interrupt handling support for 64-bit hosts. Change common stack
layout to refer PPC_LR_STKOFF kernel constant. Dispatch the 64-bit execution
flow to the existing kvm_handler_common asm macro. Update input register
values documentation.
Only the bolted version of TLB miss exception handlers is supported now.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/include/asm/kvm_booke_hv_asm.h |   12 +++-
 arch/powerpc/kvm/bookehv_interrupts.S       |  120 +++++++++++++++++++++++++--
 2 files changed, 122 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/include/asm/kvm_booke_hv_asm.h b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
index 30a600f..8be6f87 100644
--- a/arch/powerpc/include/asm/kvm_booke_hv_asm.h
+++ b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, version 2, as
@@ -17,6 +17,7 @@
  * there are no exceptions for which we fall through directly to
  * the normal host handler.
  *
+ * 32-bit host
  * Expected inputs (normal exceptions):
  *   SCRATCH0 = saved r10
  *   r10 = thread struct
@@ -33,6 +34,15 @@
  *   *(r8 + GPR9) = saved r9
  *   *(r8 + GPR10) = saved r10 (r10 not yet clobbered)
  *   *(r8 + GPR11) = saved r11
+ *
+ * 64-bit host
+ * Expected inputs (exception types GEN/DBG/CRIT/MC):
+ *  r13 = PACA_POINTER
+ *  r10 = saved CR
+ *  SPRN_SPRG_##type##_SCRATCH = saved r13
+ *  *(r13 + PACA_EX##type + EX_R10) = saved r10
+ *  *(r13 + PACA_EX##type + EX_R11) = saved r11
+ * Only the bolted version of TLB miss exception handlers is supported now.
  */
 .macro DO_KVM intno srr1
 #ifdef CONFIG_KVM_BOOKE_HV
diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S
index dff8ed4..04097de 100644
--- a/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/arch/powerpc/kvm/bookehv_interrupts.S
@@ -12,10 +12,11 @@
  * along with this program; if not, write to the Free Software
  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  *
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
  *
  * Author: Varun Sethi <varun.sethi@freescale.com>
  * Author: Scott Wood <scotwood@freescale.com>
+ * Author: Mihai Caraman <mihai.caraman@freescale.com>
  *
  * This file is derived from arch/powerpc/kvm/booke_interrupts.S
  */
@@ -30,7 +31,11 @@
 #include <asm/bitsperlong.h>
 #include <asm/thread_info.h>
 
+#ifdef CONFIG_64BIT
+#include <asm/exception-64e.h>
+#else
 #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
+#endif
 
 #define LONGBYTES		(BITS_PER_LONG / 8)
 
@@ -38,20 +43,21 @@
 #define VCPU_GUEST_SPRG(n)	(VCPU_GUEST_SPRGS + (n * LONGBYTES))
 
 /* The host stack layout: */
-#define HOST_R1         (0 * LONGBYTES) /* Implied by stwu. */
-#define HOST_CALLEE_LR  (1 * LONGBYTES)
-#define HOST_RUN        (2 * LONGBYTES) /* struct kvm_run */
+#define HOST_R1         0 /* Implied by stwu. */
+#define HOST_CALLEE_LR  PPC_LR_STKOFF
+#define HOST_RUN        (HOST_CALLEE_LR + LONGBYTES)
 /*
  * r2 is special: it holds 'current', and it made nonvolatile in the
  * kernel with the -ffixed-r2 gcc option.
  */
-#define HOST_R2         (3 * LONGBYTES)
-#define HOST_CR         (4 * LONGBYTES)
-#define HOST_NV_GPRS    (5 * LONGBYTES)
+#define HOST_R2         (HOST_RUN + LONGBYTES)
+#define HOST_CR         (HOST_R2 + LONGBYTES)
+#define HOST_NV_GPRS    (HOST_CR + LONGBYTES)
 #define HOST_NV_GPR(n)  (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
 #define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + LONGBYTES)
 #define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
-#define HOST_STACK_LR   (HOST_STACK_SIZE + LONGBYTES) /* In caller stack frame. */
+/* LR in caller stack frame. */
+#define HOST_STACK_LR	(HOST_STACK_SIZE + PPC_LR_STKOFF)
 
 #define NEED_EMU		0x00000001 /* emulation -- save nv regs */
 #define NEED_DEAR		0x00000002 /* save faulting DEAR */
@@ -202,6 +208,102 @@
 	b	kvmppc_resume_host
 .endm
 
+#ifdef CONFIG_64BIT
+/*
+ * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
+ */
+.macro kvm_handler intno scratch, paca_ex, ex_r10, ex_r11, srr0, srr1, flags
+ _GLOBAL(kvmppc_handler_\intno\()_\srr1)
+	mr	r11, r4
+	/*
+	 * Get vcpu from Paca: paca->__current.thread->kvm_vcpu
+	 */
+	PPC_LL	r4, PACACURRENT(r13)
+	PPC_LL	r4, (THREAD + THREAD_KVM_VCPU)(r4)
+	stw	r10, VCPU_CR(r4)
+	PPC_STL r11, VCPU_GPR(r4)(r4)
+	PPC_STL	r5, VCPU_GPR(r5)(r4)
+	mfspr	r5, \scratch
+	PPC_STL	r6, VCPU_GPR(r6)(r4)
+	PPC_STL	r8, VCPU_GPR(r8)(r4)
+	PPC_STL	r9, VCPU_GPR(r9)(r4)
+	PPC_STL r5, VCPU_GPR(r13)(r4)
+	PPC_LL	r6, (\paca_ex + \ex_r10)(r13)
+	PPC_LL	r8, (\paca_ex + \ex_r11)(r13)
+	PPC_STL r3, VCPU_GPR(r3)(r4)
+	PPC_STL r7, VCPU_GPR(r7)(r4)
+	PPC_STL r12, VCPU_GPR(r12)(r4)
+	PPC_STL r6, VCPU_GPR(r10)(r4)
+	PPC_STL r8, VCPU_GPR(r11)(r4)
+	mfctr	r5
+	PPC_STL	r5, VCPU_CTR(r4)
+	mfspr	r5, \srr0
+	mfspr	r6, \srr1
+	kvm_handler_common \intno, \srr0, \flags
+.endm
+
+#define EX_PARAMS(type) 	    \
+	SPRN_SPRG_##type##_SCRATCH, \
+	PACA_EX##type, 		    \
+	EX_R10, 		    \
+	EX_R11
+
+kvm_handler BOOKE_INTERRUPT_CRITICAL, EX_PARAMS(CRIT), \
+	SPRN_CSRR0, SPRN_CSRR1, 0
+kvm_handler BOOKE_INTERRUPT_MACHINE_CHECK, EX_PARAMS(MC), \
+	SPRN_MCSRR0, SPRN_MCSRR1, 0
+kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1,(NEED_EMU | NEED_DEAR | NEED_ESR)
+kvm_handler BOOKE_INTERRUPT_INST_STORAGE, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, NEED_ESR
+kvm_handler BOOKE_INTERRUPT_EXTERNAL, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, 0
+kvm_handler BOOKE_INTERRUPT_ALIGNMENT, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1,(NEED_DEAR | NEED_ESR)
+kvm_handler BOOKE_INTERRUPT_PROGRAM, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1,NEED_ESR
+kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, 0
+kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, 0
+kvm_handler BOOKE_INTERRUPT_DECREMENTER, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, 0
+kvm_handler BOOKE_INTERRUPT_FIT, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, 0
+kvm_handler BOOKE_INTERRUPT_WATCHDOG, EX_PARAMS(CRIT),\
+	SPRN_CSRR0, SPRN_CSRR1, 0
+/*
+ * Only bolted TLB miss exception handlers are supported for now
+ */
+kvm_handler BOOKE_INTERRUPT_DTLB_MISS, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
+kvm_handler BOOKE_INTERRUPT_ITLB_MISS, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, 0
+kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, 0
+kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, 0
+kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, 0
+kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, 0
+kvm_handler BOOKE_INTERRUPT_DOORBELL, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, 0
+kvm_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, EX_PARAMS(CRIT), \
+	SPRN_CSRR0, SPRN_CSRR1, 0
+kvm_handler BOOKE_INTERRUPT_HV_PRIV, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, NEED_EMU
+kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, EX_PARAMS(GEN), \
+	SPRN_SRR0, SPRN_SRR1, 0
+kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, EX_PARAMS(GEN), \
+	SPRN_GSRR0, SPRN_GSRR1, 0
+kvm_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, EX_PARAMS(CRIT), \
+	SPRN_CSRR0, SPRN_CSRR1, 0
+kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(DBG), \
+	SPRN_DSRR0, SPRN_DSRR1, 0
+kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(CRIT), \
+	SPRN_CSRR0, SPRN_CSRR1, 0
+#else
 /*
  * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
  */
@@ -296,7 +398,7 @@ kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
 	SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
 	SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
-
+#endif
 
 /* Registers:
  *  SPRG_SCRATCH0: guest r10
-- 
1.7.4.1

[RFC PATCH 16/17] KVM: PPC: e500: Silence bogus GCC warning in tlb code

[Mihai Caraman]

64-bit GCC 4.5.1 warns about an uninitialized variable which was guarded
by a flag. Initialize the variable to make it happy.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kvm/e500_tlb.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
index 3ed4e7d..6286fbd 100644
--- a/arch/powerpc/kvm/e500_tlb.c
+++ b/arch/powerpc/kvm/e500_tlb.c
@@ -412,7 +412,8 @@ static inline void kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
 	struct tlbe_ref *ref)
 {
 	struct kvm_memory_slot *slot;
-	unsigned long pfn, hva;
+	unsigned long pfn = 0; /* shut up 64-bit GCC */
+	unsigned long hva;
 	int pfnmap = 0;
 	int tsize = BOOK3E_PAGESZ_4K;
 
-- 
1.7.4.1

[RFC PATCH 17/17] KVM: PPC: booke: Fix get_tb() compile error on 64-bit

[Mihai Caraman]

Include header file for get_tb() declaration.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
 arch/powerpc/kvm/booke.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index db05692..a427031 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -36,6 +36,7 @@
 #include <asm/dbell.h>
 #include <asm/hw_irq.h>
 #include <asm/irq.h>
+#include <asm/time.h>
 
 #include "timing.h"
 #include "booke.h"
-- 
1.7.4.1

Re: [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in sregs

[Avi Kivity]

On 06/25/2012 03:26 PM, Mihai Caraman wrote:
> Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
> for 64-bit hosts.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
>  arch/powerpc/kvm/booke.c |   14 ++++++++++++++
>  1 files changed, 14 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
> index f9fa260..d15c4b5 100644
> --- a/arch/powerpc/kvm/booke.c
> +++ b/arch/powerpc/kvm/booke.c
> @@ -1052,6 +1052,9 @@ static void get_sregs_base(struct kvm_vcpu *vcpu,
>  	u64 tb = get_tb();
>  
>  	sregs->u.e.features |= KVM_SREGS_E_BASE;
> +#ifdef CONFIG_64BIT
> +	sregs->u.e.features |= KVM_SREGS_E_64;
> +#endif
>  

This is an ABI, but I see no trace of it in Documentation.

-- 
error compiling committee.c: too many arguments to function

RE: [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in sregs

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: Avi Kivity [mailto:avi@redhat.com]
> Sent: Monday, June 25, 2012 4:00 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> Subject: Re: [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in
> sregs
> 
> On 06/25/2012 03:26 PM, Mihai Caraman wrote:
> > Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs for
> > 64-bit hosts.
> >
> > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> > ---
> >  arch/powerpc/kvm/booke.c |   14 ++++++++++++++
> >  1 files changed, 14 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index
> > f9fa260..d15c4b5 100644
> > --- a/arch/powerpc/kvm/booke.c
> > +++ b/arch/powerpc/kvm/booke.c
> > @@ -1052,6 +1052,9 @@ static void get_sregs_base(struct kvm_vcpu *vcpu,
> >  	u64 tb = get_tb();
> >
> >  	sregs->u.e.features |= KVM_SREGS_E_BASE;
> > +#ifdef CONFIG_64BIT
> > +	sregs->u.e.features |= KVM_SREGS_E_64; #endif
> >
> 
> This is an ABI, but I see no trace of it in Documentation.

The ppc sregs documentation in api.txt redirects to arch/powerpc/include/asm/kvm.h.
Isn't this enough?

Mike

Re: [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in sregs

[Avi Kivity]

On 06/25/2012 04:24 PM, Caraman Mihai Claudiu-B02008 wrote:
>> -----Original Message-----
>> From: Avi Kivity [mailto:avi@redhat.com]
>> Sent: Monday, June 25, 2012 4:00 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
>> Subject: Re: [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in
>> sregs
>> 
>> On 06/25/2012 03:26 PM, Mihai Caraman wrote:
>> > Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs for
>> > 64-bit hosts.
>> >
>> > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
>> > ---
>> >  arch/powerpc/kvm/booke.c |   14 ++++++++++++++
>> >  1 files changed, 14 insertions(+), 0 deletions(-)
>> >
>> > diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index
>> > f9fa260..d15c4b5 100644
>> > --- a/arch/powerpc/kvm/booke.c
>> > +++ b/arch/powerpc/kvm/booke.c
>> > @@ -1052,6 +1052,9 @@ static void get_sregs_base(struct kvm_vcpu *vcpu,
>> >  	u64 tb = get_tb();
>> >
>> >  	sregs->u.e.features |= KVM_SREGS_E_BASE;
>> > +#ifdef CONFIG_64BIT
>> > +	sregs->u.e.features |= KVM_SREGS_E_64; #endif
>> >
>> 
>> This is an ABI, but I see no trace of it in Documentation.
> 
> The ppc sregs documentation in api.txt redirects to arch/powerpc/include/asm/kvm.h.
> Isn't this enough?

I guess it's okay.
-- 
error compiling committee.c: too many arguments to function

Re: [RFC PATCH 10/17] PowerPC: booke64: Refactor exception prolog for save/restore regs

[Benjamin Herrenschmidt]

On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
> Refactor exception prolog to allow save/restore register parameters. Add
> addition none definition for exception prolog usage.
> This is needed for exceptions like Guest Doorbell that use GSRRx regsiters
> which do not map on exception type.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
>  arch/powerpc/kernel/exceptions-64e.S |   23 ++++++++---------------
>  1 files changed, 8 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
> index 7215cc2..52aa96b 100644
> --- a/arch/powerpc/kernel/exceptions-64e.S
> +++ b/arch/powerpc/kernel/exceptions-64e.S
> @@ -35,7 +35,7 @@
>  #define	SPECIAL_EXC_FRAME_SIZE	INT_FRAME_SIZE
>  
>  /* Exception prolog code for all exceptions */
> -#define EXCEPTION_PROLOG(n, type, addition)				    \
> +#define EXCEPTION_PROLOG(n, type, srr0, srr1, addition)		     	    \
>  	mtspr	SPRN_SPRG_##type##_SCRATCH,r13;	/* get spare registers */   \
>  	mfspr	r13,SPRN_SPRG_PACA;	/* get PACA */			    \
>  	std	r10,PACA_EX##type+EX_R10(r13);				    \
> @@ -44,54 +44,47 @@
>  	addition;			/* additional code for that exc. */ \
>  	std	r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
>  	stw	r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
> -	mfspr	r11,SPRN_##type##_SRR1;/* what are we coming from */	    \
> +	mfspr	r11,srr1;/* what are we coming from */	    		    \
>  	type##_SET_KSTACK;		/* get special stack if necessary */\
>  	andi.	r10,r11,MSR_PR;		/* save stack pointer */	    \
>  	beq	1f;			/* branch around if supervisor */   \
>  	ld	r1,PACAKSAVE(r13);	/* get kernel stack coming from usr */\
>  1:	cmpdi	cr1,r1,0;		/* check if SP makes sense */	    \
>  	bge-	cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
> -	mfspr	r10,SPRN_##type##_SRR0;	/* read SRR0 before touching stack */
> +	mfspr	r10,srr0;		/* read SRR0 before touching stack */

No, use the existing macro, use a ##type## specific to guest doorbells,
with appropriate definitions of the corresponding SPRN_ macros.

Cheers,
Ben.

Re: [RFC PATCH 11/17] PowerPC: booke64: Fix machine check handler to use the right prolog

[Benjamin Herrenschmidt]

On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
> Machine check exception handler was using a wrong prolog. Hypervisors, like
> KVM, which are called early from the exception handler rely on the interrupt
> source.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>

Ack.

Please separate your "core" patches from your KVM series and submit them
separately. I'll take care of the core Book3E part.

Cheers,
Ben.

> ---
>  arch/powerpc/kernel/exceptions-64e.S |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
> index 52aa96b..06f7aec 100644
> --- a/arch/powerpc/kernel/exceptions-64e.S
> +++ b/arch/powerpc/kernel/exceptions-64e.S
> @@ -290,7 +290,7 @@ interrupt_end_book3e:
>  
>  /* Machine Check Interrupt */
>  	START_EXCEPTION(machine_check);
> -	CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
> +	MC_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
>  //	EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE)
>  //	bl	special_reg_save_mc
>  //	addi	r3,r1,STACK_FRAME_OVERHEAD

Re: [RFC PATCH 13/17] PowerPC: booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int

[Benjamin Herrenschmidt]

On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
> Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
> Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
> SPRG4-7 registers will be clobbered.
> For bolted TLB miss exception handlers, which is the version currently
> supported by KVM, use SPRN_SPRG_GEN_SCRATCH (aka SPRG0) instead of
> SPRN_SPRG_TLB_SCRATCH (aka SPRG6) and replace TLB with GEN PACA slots to
> keep consitency.
> For critical exception handler use SPRG3 instead of SPRG7.

Beware with SPRG3 usage. It's user space visible and we plan to use it
for other things (see Anton's patch to stick topology information in
there for use by the vdso). If you clobber it, you may want to restore
it later.

I think Anton's patch should put the "proper" value we want in the PACA
anyway since we also need to restore it on exit from KVM, so you can
still use it as scratch, just restore the value before going to C.

Cheers,
Ben.

> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
>  arch/powerpc/include/asm/exception-64e.h |   14 +++++++-------
>  arch/powerpc/include/asm/reg.h           |    6 +++---
>  arch/powerpc/mm/tlb_low_64e.S            |   28 ++++++++++++++--------------
>  3 files changed, 24 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h
> index ac13add..c90a9a4 100644
> --- a/arch/powerpc/include/asm/exception-64e.h
> +++ b/arch/powerpc/include/asm/exception-64e.h
> @@ -38,8 +38,11 @@
>   */
>  
> 
> -/* We are out of SPRGs so we save some things in the PACA. The normal
> - * exception frame is smaller than the CRIT or MC one though
> +/* We are out of SPRGs so we save some things in the 8 slots available in PACA.
> + * The normal exception frame is smaller than the CRIT or MC one though
> + *
> + * Bolted TLB miss exception variant also uses these slots which in combination
> + * with pgd and kernel_pgd fits in one 64-byte cache line.
>   */
>  #define EX_R1		(0 * 8)
>  #define EX_CR		(1 * 8)
> @@ -47,13 +50,10 @@
>  #define EX_R11		(3 * 8)
>  #define EX_R14		(4 * 8)
>  #define EX_R15		(5 * 8)
> +#define EX_R16		(6 * 8)
>  
>  /*
> - * The TLB miss exception uses different slots.
> - *
> - * The bolted variant uses only the first six fields,
> - * which in combination with pgd and kernel_pgd fits in
> - * one 64-byte cache line.
> + * PACA slots offset for standard TLB miss exception.
>   */
>  
>  #define EX_TLB_R10	( 0 * 8)
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index f0cb7f4..51c14a7 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -760,10 +760,10 @@
>   * 64-bit embedded
>   *	- SPRG0 generic exception scratch
>   *	- SPRG2 TLB exception stack
> - *	- SPRG3 unused (user visible)
> + *	- SPRG3 critical exception scratch (user visible)
>   *	- SPRG4 unused (user visible)
>   *	- SPRG6 TLB miss scratch (user visible, sorry !)
> - *	- SPRG7 critical exception scratch
> + *	- SPRG7 unused (user visible)
>   *	- SPRG8 machine check exception scratch
>   *	- SPRG9 debug exception scratch
>   *
> @@ -857,7 +857,7 @@
>  
>  #ifdef CONFIG_PPC_BOOK3E_64
>  #define SPRN_SPRG_MC_SCRATCH	SPRN_SPRG8
> -#define SPRN_SPRG_CRIT_SCRATCH	SPRN_SPRG7
> +#define SPRN_SPRG_CRIT_SCRATCH	SPRN_SPRG3
>  #define SPRN_SPRG_DBG_SCRATCH	SPRN_SPRG9
>  #define SPRN_SPRG_TLB_EXFRAME	SPRN_SPRG2
>  #define SPRN_SPRG_TLB_SCRATCH	SPRN_SPRG6
> diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
> index 88feaaa..4192ade 100644
> --- a/arch/powerpc/mm/tlb_low_64e.S
> +++ b/arch/powerpc/mm/tlb_low_64e.S
> @@ -40,36 +40,36 @@
>   **********************************************************************/
>  
>  .macro tlb_prolog_bolted intnum addr
> -	mtspr	SPRN_SPRG_TLB_SCRATCH,r13
> +	mtspr	SPRN_SPRG_GEN_SCRATCH,r13
>  	mfspr	r13,SPRN_SPRG_PACA
> -	std	r10,PACA_EXTLB+EX_TLB_R10(r13)
> +	std	r10,PACA_EXGEN+EX_R10(r13)
>  	mfcr	r10
> -	std	r11,PACA_EXTLB+EX_TLB_R11(r13)
> +	std	r11,PACA_EXGEN+EX_R11(r13)
>  #ifdef CONFIG_KVM_BOOKE_HV
>  BEGIN_FTR_SECTION
>  	mfspr	r11, SPRN_SRR1
>  END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
>  #endif
>  	DO_KVM	\intnum, SPRN_SRR1
> -	std	r16,PACA_EXTLB+EX_TLB_R16(r13)
> +	std	r16,PACA_EXGEN+EX_R16(r13)
>  	mfspr	r16,\addr		/* get faulting address */
> -	std	r14,PACA_EXTLB+EX_TLB_R14(r13)
> +	std	r14,PACA_EXGEN+EX_R14(r13)
>  	ld	r14,PACAPGD(r13)
> -	std	r15,PACA_EXTLB+EX_TLB_R15(r13)
> -	std	r10,PACA_EXTLB+EX_TLB_CR(r13)
> +	std	r15,PACA_EXGEN+EX_R15(r13)
> +	std	r10,PACA_EXGEN+EX_CR(r13)
>  	TLB_MISS_PROLOG_STATS_BOLTED
>  .endm
>  
>  .macro tlb_epilog_bolted
> -	ld	r14,PACA_EXTLB+EX_TLB_CR(r13)
> -	ld	r10,PACA_EXTLB+EX_TLB_R10(r13)
> -	ld	r11,PACA_EXTLB+EX_TLB_R11(r13)
> +	ld	r14,PACA_EXGEN+EX_CR(r13)
> +	ld	r10,PACA_EXGEN+EX_R10(r13)
> +	ld	r11,PACA_EXGEN+EX_R11(r13)
>  	mtcr	r14
> -	ld	r14,PACA_EXTLB+EX_TLB_R14(r13)
> -	ld	r15,PACA_EXTLB+EX_TLB_R15(r13)
> +	ld	r14,PACA_EXGEN+EX_R14(r13)
> +	ld	r15,PACA_EXGEN+EX_R15(r13)
>  	TLB_MISS_RESTORE_STATS_BOLTED
> -	ld	r16,PACA_EXTLB+EX_TLB_R16(r13)
> -	mfspr	r13,SPRN_SPRG_TLB_SCRATCH
> +	ld	r16,PACA_EXGEN+EX_R16(r13)
> +	mfspr	r13,SPRN_SPRG_GEN_SCRATCH
>  .endm
>  
>  /* Data TLB miss */

Re: [RFC PATCH 13/17] PowerPC: booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int

[Scott Wood]

On 06/25/2012 07:26 AM, Mihai Caraman wrote:
> Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
> Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
> SPRG4-7 registers will be clobbered.
> For bolted TLB miss exception handlers, which is the version currently
> supported by KVM, use SPRN_SPRG_GEN_SCRATCH (aka SPRG0) instead of
> SPRN_SPRG_TLB_SCRATCH (aka SPRG6) and replace TLB with GEN PACA slots to
> keep consitency.
> For critical exception handler use SPRG3 instead of SPRG7.

extlb is in the same cache line as other TLB stuff we need, while exgen
isn't.  Let's stick with extlb.

-Scott

Re: [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in sregs

[Scott Wood]

On 06/25/2012 07:26 AM, Mihai Caraman wrote:
> Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
> for 64-bit hosts.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
>  arch/powerpc/kvm/booke.c |   14 ++++++++++++++
>  1 files changed, 14 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
> index f9fa260..d15c4b5 100644
> --- a/arch/powerpc/kvm/booke.c
> +++ b/arch/powerpc/kvm/booke.c
> @@ -1052,6 +1052,9 @@ static void get_sregs_base(struct kvm_vcpu *vcpu,
>  	u64 tb = get_tb();
>  
>  	sregs->u.e.features |= KVM_SREGS_E_BASE;
> +#ifdef CONFIG_64BIT
> +	sregs->u.e.features |= KVM_SREGS_E_64;0
> +#endif
>  
>  	sregs->u.e.csrr0 = vcpu->arch.csrr0;
>  	sregs->u.e.csrr1 = vcpu->arch.csrr1;
> @@ -1063,6 +1066,9 @@ static void get_sregs_base(struct kvm_vcpu *vcpu,
>  	sregs->u.e.dec = kvmppc_get_dec(vcpu, tb);
>  	sregs->u.e.tb = tb;
>  	sregs->u.e.vrsave = vcpu->arch.vrsave;
> +#ifdef CONFIG_64BIT
> +	sregs->u.e.epcr = vcpu->arch.epcr;
> +#endif
>  }
>  
>  static int set_sregs_base(struct kvm_vcpu *vcpu,
> @@ -1071,6 +1077,11 @@ static int set_sregs_base(struct kvm_vcpu *vcpu,
>  	if (!(sregs->u.e.features & KVM_SREGS_E_BASE))
>  		return 0;
>  
> +#ifdef CONFIG_64BIT
> +	if (!(sregs->u.e.features & KVM_SREGS_E_64))
> +		return 0;
> +#endif

This means that a QEMU targeting a 32-bit guest won't be able to set any
special registers, if it sets feature bits manually rather than getting
them from GET_SREGS.

This check should only qualify whether we look at sregs.u.e.epcr, not
whether this function works at all.

BTW, shouldn't the BASE check return an error rather than silently no-op?

-Scott

RE: [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in sregs

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Wednesday, June 27, 2012 1:35 AM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> Subject: Re: [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in
> sregs
> 
> On 06/25/2012 07:26 AM, Mihai Caraman wrote:
> > Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs for
> > 64-bit hosts.
> >
> > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> > ---
> >  arch/powerpc/kvm/booke.c |   14 ++++++++++++++
> >  1 files changed, 14 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index
> > f9fa260..d15c4b5 100644
> > --- a/arch/powerpc/kvm/booke.c
> > +++ b/arch/powerpc/kvm/booke.c
> > @@ -1052,6 +1052,9 @@ static void get_sregs_base(struct kvm_vcpu *vcpu,
> >  	u64 tb = get_tb();
> >
> >  	sregs->u.e.features |= KVM_SREGS_E_BASE;
> > +#ifdef CONFIG_64BIT
> > +	sregs->u.e.features |= KVM_SREGS_E_64;0 #endif
> >
> >  	sregs->u.e.csrr0 = vcpu->arch.csrr0;
> >  	sregs->u.e.csrr1 = vcpu->arch.csrr1; @@ -1063,6 +1066,9 @@ static
> > void get_sregs_base(struct kvm_vcpu *vcpu,
> >  	sregs->u.e.dec = kvmppc_get_dec(vcpu, tb);
> >  	sregs->u.e.tb = tb;
> >  	sregs->u.e.vrsave = vcpu->arch.vrsave;
> > +#ifdef CONFIG_64BIT
> > +	sregs->u.e.epcr = vcpu->arch.epcr;
> > +#endif
> >  }
> >
> >  static int set_sregs_base(struct kvm_vcpu *vcpu, @@ -1071,6 +1077,11
> > @@ static int set_sregs_base(struct kvm_vcpu *vcpu,
> >  	if (!(sregs->u.e.features & KVM_SREGS_E_BASE))
> >  		return 0;
> >
> > +#ifdef CONFIG_64BIT
> > +	if (!(sregs->u.e.features & KVM_SREGS_E_64))
> > +		return 0;
> > +#endif
> 
> This means that a QEMU targeting a 32-bit guest won't be able to set any
> special registers, if it sets feature bits manually rather than getting
> them from GET_SREGS.

I had some concerns about his. I only check qemu ppc code which uses get/set
approach and I followed the BASE model. Now I see that qemu x86 set them manually :(
Why do we care if the caller set or not BASE?

-Mike

RE: [RFC PATCH 10/17] PowerPC: booke64: Refactor exception prolog for save/restore regs

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> Sent: Wednesday, June 27, 2012 1:13 AM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> Subject: Re: [RFC PATCH 10/17] PowerPC: booke64: Refactor exception
> prolog for save/restore regs
> 
> On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
> > Refactor exception prolog to allow save/restore register parameters.
> > Add addition none definition for exception prolog usage.
> > This is needed for exceptions like Guest Doorbell that use GSRRx
> > regsiters which do not map on exception type.
> >
> > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> > ---
> >  arch/powerpc/kernel/exceptions-64e.S |   23 ++++++++---------------
> >  1 files changed, 8 insertions(+), 15 deletions(-)
> >
> > diff --git a/arch/powerpc/kernel/exceptions-64e.S
> > b/arch/powerpc/kernel/exceptions-64e.S
> > index 7215cc2..52aa96b 100644
> > --- a/arch/powerpc/kernel/exceptions-64e.S
> > +++ b/arch/powerpc/kernel/exceptions-64e.S
> > @@ -35,7 +35,7 @@
> >  #define	SPECIAL_EXC_FRAME_SIZE	INT_FRAME_SIZE
> >
> >  /* Exception prolog code for all exceptions */
> > -#define EXCEPTION_PROLOG(n, type, addition)				    \
> > +#define EXCEPTION_PROLOG(n, type, srr0, srr1, addition)
> \
> >  	mtspr	SPRN_SPRG_##type##_SCRATCH,r13;	/* get spare registers */
> \
> >  	mfspr	r13,SPRN_SPRG_PACA;	/* get PACA */			    \
> >  	std	r10,PACA_EX##type+EX_R10(r13);				    \
> > @@ -44,54 +44,47 @@
> >  	addition;			/* additional code for that exc. */ \
> >  	std	r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
> >  	stw	r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
> > -	mfspr	r11,SPRN_##type##_SRR1;/* what are we coming from */	    \
> > +	mfspr	r11,srr1;/* what are we coming from */	    		    \
> >  	type##_SET_KSTACK;		/* get special stack if necessary */\
> >  	andi.	r10,r11,MSR_PR;		/* save stack pointer */	    \
> >  	beq	1f;			/* branch around if supervisor */   \
> >  	ld	r1,PACAKSAVE(r13);	/* get kernel stack coming from usr
> */\
> >  1:	cmpdi	cr1,r1,0;		/* check if SP makes sense */	    \
> >  	bge-	cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
> > -	mfspr	r10,SPRN_##type##_SRR0;	/* read SRR0 before touching stack */
> > +	mfspr	r10,srr0;		/* read SRR0 before touching stack */
> 
> No, use the existing macro, use a ##type## specific to guest doorbells,
> with appropriate definitions of the corresponding SPRN_ macros.

I assume that specific PACA_EX, SCRATCH and SET_KSTACK definitions will
fallback to GEN.

Cheers,
Mike

Re: [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in sregs

[Scott Wood]

On 06/27/2012 06:41 AM, Caraman Mihai Claudiu-B02008 wrote:
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Wednesday, June 27, 2012 1:35 AM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
>> Subject: Re: [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in
>> sregs
>>
>> On 06/25/2012 07:26 AM, Mihai Caraman wrote:
>>> Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs for
>>> 64-bit hosts.
>>>
>>> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
>>> ---
>>>  arch/powerpc/kvm/booke.c |   14 ++++++++++++++
>>>  1 files changed, 14 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c index
>>> f9fa260..d15c4b5 100644
>>> --- a/arch/powerpc/kvm/booke.c
>>> +++ b/arch/powerpc/kvm/booke.c
>>> @@ -1052,6 +1052,9 @@ static void get_sregs_base(struct kvm_vcpu *vcpu,
>>>  	u64 tb = get_tb();
>>>
>>>  	sregs->u.e.features |= KVM_SREGS_E_BASE;
>>> +#ifdef CONFIG_64BIT
>>> +	sregs->u.e.features |= KVM_SREGS_E_64;0 #endif
>>>
>>>  	sregs->u.e.csrr0 = vcpu->arch.csrr0;
>>>  	sregs->u.e.csrr1 = vcpu->arch.csrr1; @@ -1063,6 +1066,9 @@ static
>>> void get_sregs_base(struct kvm_vcpu *vcpu,
>>>  	sregs->u.e.dec = kvmppc_get_dec(vcpu, tb);
>>>  	sregs->u.e.tb = tb;
>>>  	sregs->u.e.vrsave = vcpu->arch.vrsave;
>>> +#ifdef CONFIG_64BIT
>>> +	sregs->u.e.epcr = vcpu->arch.epcr;
>>> +#endif
>>>  }
>>>
>>>  static int set_sregs_base(struct kvm_vcpu *vcpu, @@ -1071,6 +1077,11
>>> @@ static int set_sregs_base(struct kvm_vcpu *vcpu,
>>>  	if (!(sregs->u.e.features & KVM_SREGS_E_BASE))
>>>  		return 0;
>>>
>>> +#ifdef CONFIG_64BIT
>>> +	if (!(sregs->u.e.features & KVM_SREGS_E_64))
>>> +		return 0;
>>> +#endif
>>
>> This means that a QEMU targeting a 32-bit guest won't be able to set any
>> special registers, if it sets feature bits manually rather than getting
>> them from GET_SREGS.
> 
> I had some concerns about his. I only check qemu ppc code which uses get/set
> approach and I followed the BASE model. Now I see that qemu x86 set them manually :(
> Why do we care if the caller set or not BASE?

BASE contains things which should be present on all booke chips.  If
that's not set something's wrong.

None of the other feature bits are handled that way.

-Scott

Re: [RFC PATCH 02/17] KVM: PPC64: booke: Add EPCR support in mtspr/mfspr emulation

[Alexander Graf]

On 25.06.2012, at 14:26, Mihai Caraman wrote:

> Add EPCR support in booke mtspr/mfspr emulation. EPCR register is defined
> only for 64-bit and HV categories, so it shoud be available only on 64-bit
> virtual processors. Undefine the support for 32-bit builds.
> Define a reusable setter function for vcpu's EPCR.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
> arch/powerpc/kvm/booke.c         |   12 +++++++++++-
> arch/powerpc/kvm/booke.h         |    6 ++++++
> arch/powerpc/kvm/booke_emulate.c |   13 ++++++++++++-
> 3 files changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
> index 72f13f4..f9fa260 100644
> --- a/arch/powerpc/kvm/booke.c
> +++ b/arch/powerpc/kvm/booke.c
> @@ -13,7 +13,7 @@
>  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
>  *
>  * Copyright IBM Corp. 2007
> - * Copyright 2010-2011 Freescale Semiconductor, Inc.
> + * Copyright 2010-2012 Freescale Semiconductor, Inc.
>  *
>  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
>  *          Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
> @@ -1243,6 +1243,16 @@ void kvmppc_core_commit_memory_region(struct kvm *kvm,
> {
> }
> 
> +#ifdef CONFIG_64BIT
> +void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr)
> +{
> +	vcpu->arch.epcr = new_epcr;
> +	vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM;
> +	if (vcpu->arch.epcr  & SPRN_EPCR_ICM)
> +		vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM;

Why would the setter be #ifdef CONFIG_64BIT? EPCR exists on e500mc too, no? Please only #ifdef the GICM bits out.


Alex

Re: [RFC PATCH 01/17] KVM: PPC64: booke: Set interrupt computation mode for 64-bit host

[Alexander Graf]

On 25.06.2012, at 14:26, Mihai Caraman wrote:

> 64-bit host needs to remain in 64-bit mode when an exception take place.
> Set interrupt computaion mode in EPCR register.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>

Thanks, applied to kvm-ppc-next.


Alex

Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in sregs

[Alexander Graf]

On 25.06.2012, at 14:26, Mihai Caraman wrote:

> Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
> for 64-bit hosts.

Please also implement a ONE_REG interface while at it. Over time, I'd like to move towards ONE_REG instead of the messy regs/sregs API.


Alex

Re: [Qemu-ppc] [RFC PATCH 04/17] KVM: PPC64: booke: Add guest computation mode for irq delivery

[Alexander Graf]

On 25.06.2012, at 14:26, Mihai Caraman wrote:

> When delivering guest IRQs, update MSR computaion

computation

> mode according to guest
> interrupt computation mode found in EPCR.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
> arch/powerpc/kvm/booke.c |    8 +++++++-
> 1 files changed, 7 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
> index d15c4b5..93b48e0 100644
> --- a/arch/powerpc/kvm/booke.c
> +++ b/arch/powerpc/kvm/booke.c
> @@ -287,6 +287,7 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
> 	bool crit;
> 	bool keep_irq = false;
> 	enum int_class int_class;
> +	ulong msr_cm = 0;
> 
> 	/* Truncate crit indicators in 32 bit mode */
> 	if (!(vcpu->arch.shared->msr & MSR_SF)) {
> @@ -299,6 +300,10 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
> 	/* ... and we're in supervisor mode */
> 	crit = crit && !(vcpu->arch.shared->msr & MSR_PR);
> 
> +#ifdef CONFIG_64BIT
> +	msr_cm = vcpu->arch.epcr & SPRN_EPCR_ICM ? MSR_CM : 0;
> +#endif

No need for the ifdef, no?. Just mask EPCR_ICM out in the 32-bit host case, then this check is always false on 32-bit hosts.

> +
> 	if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) {
> 		priority = BOOKE_IRQPRIO_EXTERNAL;
> 		keep_irq = true;
> @@ -381,7 +386,8 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
> 			set_guest_esr(vcpu, vcpu->arch.queued_esr);
> 		if (update_dear == true)
> 			set_guest_dear(vcpu, vcpu->arch.queued_dear);
> -		kvmppc_set_msr(vcpu, vcpu->arch.shared->msr & msr_mask);
> +		kvmppc_set_msr(vcpu, (vcpu->arch.shared->msr & msr_mask)
> +				| msr_cm);

Please split this computation out into its own variable and apply the masking regardless. Something like

ulong new_msr = vcpu->arch.shared->msr;
if (vcpu->arch.epcr & SPRN_EPCR_ICM)
    new_msr |= MSR_CM;
new_msr &= msr_mask;
kvmppc_set_msr(vcpu, new_msr);

Alex

Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2 EPN mask for 64-bit

[Alexander Graf]

On 25.06.2012, at 14:26, Mihai Caraman wrote:

> Extend MAS2 EPN mask for 64-bit hosts, to retain most significant bits.
> Change get tlb eaddr to use this mask.

Please see section 6.11.4.8 in the PowerISA 2.06b:

MMU behavior is largely unaffected by whether the thread is in 32-bit computation mode (MSRCM=0) or 64- bit computation mode (MSRCM=1). The only differ- ences occur in the EPN field of the TLB entry and the EPN field of MAS2. The differences are summarized here.

	•  Executing a tlbwe instruction in 32-bit mode will set bits 0:31 of the TLB EPN field to zero unless MAS0ATSEL is set, in which case those bits are not written to zero.
	•  In 32-bit implementations, MAS2U can be used to read or write EPN0:31 of MAS2.

So if MSR.CM is not set tlbwe should mask the upper 32 bits out - which can happen regardless of CONFIG_64BIT.
Also, we need to implement MAS2U, to potentially make the upper 32bits of MAS2 available, right? But that one isn't as important as the first bit.


Alex

Re: [RFC PATCH 06/17] KVM: PPC: e500: Add emulation helper for getting instruction ea

[Alexander Graf]

On 25.06.2012, at 14:26, Mihai Caraman wrote:

> Add emulation helper for getting instruction ea and refactor tlb instruction
> emulation to use it.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
> arch/powerpc/kvm/e500.h         |    6 +++---
> arch/powerpc/kvm/e500_emulate.c |   21 ++++++++++++++++++---
> arch/powerpc/kvm/e500_tlb.c     |   23 ++++++-----------------
> 3 files changed, 27 insertions(+), 23 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
> index 3e31098..70bfed4 100644
> --- a/arch/powerpc/kvm/e500.h
> +++ b/arch/powerpc/kvm/e500.h
> @@ -130,9 +130,9 @@ int kvmppc_e500_emul_mt_mmucsr0(struct kvmppc_vcpu_e500 *vcpu_e500,
> 				ulong value);
> int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu);
> int kvmppc_e500_emul_tlbre(struct kvm_vcpu *vcpu);
> -int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, int ra, int rb);
> -int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, int ra, int rb);
> -int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, int rb);
> +int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, gva_t ea);
> +int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, gva_t ea);
> +int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, gva_t ea);
> int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 *vcpu_e500);
> void kvmppc_e500_tlb_uninit(struct kvmppc_vcpu_e500 *vcpu_e500);
> 
> diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
> index 8b99e07..81288f7 100644
> --- a/arch/powerpc/kvm/e500_emulate.c
> +++ b/arch/powerpc/kvm/e500_emulate.c
> @@ -82,6 +82,17 @@ static int kvmppc_e500_emul_msgsnd(struct kvm_vcpu *vcpu, int rb)
> }
> #endif
> 
> +static inline ulong kvmppc_get_ea_indexed(struct kvm_vcpu *vcpu, int ra, int rb)
> +{
> +	ulong ea;
> +
> +	ea = kvmppc_get_gpr(vcpu, rb);
> +	if (ra)
> +		ea += kvmppc_get_gpr(vcpu, ra);
> +
> +	return ea;
> +}
> +

Please move this one to arch/powerpc/include/asm/kvm_ppc.h.

> int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
>                            unsigned int inst, int *advance)
> {
> @@ -89,6 +100,7 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
> 	int ra = get_ra(inst);
> 	int rb = get_rb(inst);
> 	int rt = get_rt(inst);
> +	gva_t ea;
> 
> 	switch (get_op(inst)) {
> 	case 31:
> @@ -113,15 +125,18 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
> 			break;
> 
> 		case XOP_TLBSX:
> -			emulated = kvmppc_e500_emul_tlbsx(vcpu,rb);
> +			ea = kvmppc_get_ea_indexed(vcpu, ra, rb);
> +			emulated = kvmppc_e500_emul_tlbsx(vcpu, ea);
> 			break;
> 
> 		case XOP_TLBILX:
> -			emulated = kvmppc_e500_emul_tlbilx(vcpu, rt, ra, rb);
> +			ea = kvmppc_get_ea_indexed(vcpu, ra, rb);
> +			emulated = kvmppc_e500_emul_tlbilx(vcpu, rt, ea);

What's the point in hiding ra+rb, but not rt? I like the idea of hiding the register semantics, but please move rt into a local variable that gets passed as pointer to kvmppc_e500_emul_tlbilx.


Alex

Re: [Qemu-ppc] [RFC PATCH 07/17] KVM: PPC: e500: Mask ea's high 32-bits in 32/64 instr emulation

[Alexander Graf]

On 25.06.2012, at 14:26, Mihai Caraman wrote:

> Mask high 32 bits of effective address in emulation layer, for guests running
> in 32-bit mode.
> MAS2's high-order 32 bits represents the upper 32 bits of the effective address
> of the page. Mask it too for tlbwe instruction emulation.

Ah, there is the tlbwe masking :). Please split this into 2 patches.

> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
> arch/powerpc/kvm/e500_emulate.c |    5 ++++-
> arch/powerpc/kvm/e500_tlb.c     |    2 ++
> 2 files changed, 6 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
> index 81288f7..94305db 100644
> --- a/arch/powerpc/kvm/e500_emulate.c
> +++ b/arch/powerpc/kvm/e500_emulate.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
> + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. All rights reserved.
>  *
>  * Author: Yu Liu, <yu.liu@freescale.com>
>  *
> @@ -90,6 +90,9 @@ static inline ulong kvmppc_get_ea_indexed(struct kvm_vcpu *vcpu, int ra, int rb)
> 	if (ra)
> 		ea += kvmppc_get_gpr(vcpu, ra);
> 
> +	if (!(vcpu->arch.shared->msr & MSR_CM))
> +		ea &= 0xffffffffUL;

Since this will be in generic code, please guard it with an #ifdef CONFIG_BOOKE.


Alex

Re: [Qemu-ppc] [RFC PATCH 07/17] KVM: PPC: e500: Mask ea's high 32-bits in 32/64 instr emulation

[Alexander Graf]

On 04.07.2012, at 16:00, Alexander Graf wrote:

> 
> On 25.06.2012, at 14:26, Mihai Caraman wrote:
> 
>> Mask high 32 bits of effective address in emulation layer, for guests running
>> in 32-bit mode.
>> MAS2's high-order 32 bits represents the upper 32 bits of the effective address
>> of the page. Mask it too for tlbwe instruction emulation.
> 
> Ah, there is the tlbwe masking :). Please split this into 2 patches.
> 
>> 
>> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
>> ---
>> arch/powerpc/kvm/e500_emulate.c |    5 ++++-
>> arch/powerpc/kvm/e500_tlb.c     |    2 ++
>> 2 files changed, 6 insertions(+), 1 deletions(-)
>> 
>> diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
>> index 81288f7..94305db 100644
>> --- a/arch/powerpc/kvm/e500_emulate.c
>> +++ b/arch/powerpc/kvm/e500_emulate.c
>> @@ -1,5 +1,5 @@
>> /*
>> - * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
>> + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. All rights reserved.
>> *
>> * Author: Yu Liu, <yu.liu@freescale.com>
>> *
>> @@ -90,6 +90,9 @@ static inline ulong kvmppc_get_ea_indexed(struct kvm_vcpu *vcpu, int ra, int rb)
>> 	if (ra)
>> 		ea += kvmppc_get_gpr(vcpu, ra);
>> 
>> +	if (!(vcpu->arch.shared->msr & MSR_CM))
>> +		ea &= 0xffffffffUL;
> 
> Since this will be in generic code, please guard it with an #ifdef CONFIG_BOOKE.

Oh and do the same check for MSR_SF on Book3s :). Maybe something like

ulong msr_64bit = 0;

#if defined(CONFIG_PPC_BOOK3E_64)
msr_64bit = MSR_CM;
#elif defined(CONFIG_PPC_BOOK3S_64)
msr_64bit = MSR_SF;
#endif

if (!(vcpu->arch.shared->msr & msr_64bit))
    ea = (uint32_t)ea;


Alex

RE: [RFC PATCH 02/17] KVM: PPC64: booke: Add EPCR support in mtspr/mfspr emulation

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
> owner@vger.kernel.org] On Behalf Of Alexander Graf
> Sent: Wednesday, July 04, 2012 4:22 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> Subject: Re: [RFC PATCH 02/17] KVM: PPC64: booke: Add EPCR support in
> mtspr/mfspr emulation
> 
> 
> On 25.06.2012, at 14:26, Mihai Caraman wrote:
> 
> > Add EPCR support in booke mtspr/mfspr emulation. EPCR register is
> defined
> > only for 64-bit and HV categories, so it shoud be available only on 64-
> bit
> > virtual processors. Undefine the support for 32-bit builds.
> > Define a reusable setter function for vcpu's EPCR.
> >
> > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> > ---
> > arch/powerpc/kvm/booke.c         |   12 +++++++++++-
> > arch/powerpc/kvm/booke.h         |    6 ++++++
> > arch/powerpc/kvm/booke_emulate.c |   13 ++++++++++++-
> > 3 files changed, 29 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
> > index 72f13f4..f9fa260 100644
> > --- a/arch/powerpc/kvm/booke.c
> > +++ b/arch/powerpc/kvm/booke.c
> > @@ -13,7 +13,7 @@
> >  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
> USA.
> >  *
> >  * Copyright IBM Corp. 2007
> > - * Copyright 2010-2011 Freescale Semiconductor, Inc.
> > + * Copyright 2010-2012 Freescale Semiconductor, Inc.
> >  *
> >  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
> >  *          Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
> > @@ -1243,6 +1243,16 @@ void kvmppc_core_commit_memory_region(struct kvm
> *kvm,
> > {
> > }
> >
> > +#ifdef CONFIG_64BIT
> > +void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr)
> > +{
> > +	vcpu->arch.epcr = new_epcr;
> > +	vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM;
> > +	if (vcpu->arch.epcr  & SPRN_EPCR_ICM)
> > +		vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM;
> 
> Why would the setter be #ifdef CONFIG_64BIT? EPCR exists on e500mc too,
> no? Please only #ifdef the GICM bits out.

kvmppc_set_epcr deals with guest EPCR and EPCR does not exist on a virtual e500mc
as detailed in patch's comment. All callers are also guarded by #ifdef CONFIG_64BIT,
my assumption was that we will not support a virtual core with 64-bit category
on a 32-bit host.

> 
> 
> Alex
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [Qemu-ppc] [RFC PATCH 09/17] KVM: PPC64: booke: Hard disable interrupts when entering guest

[Alexander Graf]

On 25.06.2012, at 14:26, Mihai Caraman wrote:

> 64-bit host runs with lazy interrupt disabling, so local_irq_disable() does
> not disable interrupts right away and does not protect against preemption
> required by __kvmppc_vcpu_run(). Define a macro for 64-bit to use
> hard_irq_disable().
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
> arch/powerpc/kvm/booke.c |   14 ++++++++++----
> 1 files changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
> index 93b48e0..db05692 100644
> --- a/arch/powerpc/kvm/booke.c
> +++ b/arch/powerpc/kvm/booke.c
> @@ -45,6 +45,12 @@ unsigned long kvmppc_booke_handlers;
> #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
> #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
> 
> +#ifdef CONFIG_64BIT
> +#define _hard_irq_disable() hard_irq_disable()
> +#else
> +#define _hard_irq_disable() local_irq_disable()
> +#endif

So you only swap out the disable bit, but not the enable one? Ben, would this work out?


Alex

> +
> struct kvm_stats_debugfs_item debugfs_entries[] = {
> 	{ "mmio",       VCPU_STAT(mmio_exits) },
> 	{ "dcr",        VCPU_STAT(dcr_exits) },
> @@ -456,7 +462,7 @@ int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu)
> 		local_irq_enable();
> 		kvm_vcpu_block(vcpu);
> 		clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
> -		local_irq_disable();
> +		_hard_irq_disable();
> 
> 		kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS);
> 		r = 1;
> @@ -480,7 +486,7 @@ static int kvmppc_prepare_to_enter(struct kvm_vcpu *vcpu)
> 		if (need_resched()) {
> 			local_irq_enable();
> 			cond_resched();
> -			local_irq_disable();
> +			_hard_irq_disable();
> 			continue;
> 		}
> 
> @@ -515,7 +521,7 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
> 		return -EINVAL;
> 	}
> 
> -	local_irq_disable();
> +	_hard_irq_disable();
> 	if (kvmppc_prepare_to_enter(vcpu)) {
> 		kvm_run->exit_reason = KVM_EXIT_INTR;
> 		ret = -EINTR;
> @@ -955,7 +961,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
> 	 * aren't already exiting to userspace for some other reason.
> 	 */
> 	if (!(r & RESUME_HOST)) {
> -		local_irq_disable();
> +		_hard_irq_disable();
> 		if (kvmppc_prepare_to_enter(vcpu)) {
> 			run->exit_reason = KVM_EXIT_INTR;
> 			r = (-EINTR << 2) | RESUME_HOST | (r & RESUME_FLAG_NV);
> -- 
> 1.7.4.1
> 
> 
> 

Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Alexander Graf]

On 25.06.2012, at 14:26, Mihai Caraman wrote:

> Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit booke
> see head_fsl_booke.S file. Extend interrupt handlers' parameter list with
> interrupt vector numbers to accomodate the macro. Rework Guest Doorbell
> handler to use the proper GSRRx save/restore registers.
> Only the bolted version of tlb miss handers is addressed now.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
> arch/powerpc/kernel/exceptions-64e.S |  114 ++++++++++++++++++++++++----------
> arch/powerpc/mm/tlb_low_64e.S        |   14 +++-
> 2 files changed, 92 insertions(+), 36 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
> index 06f7aec..a60f81f 100644
> --- a/arch/powerpc/kernel/exceptions-64e.S
> +++ b/arch/powerpc/kernel/exceptions-64e.S
> @@ -25,6 +25,8 @@
> #include <asm/ppc-opcode.h>
> #include <asm/mmu.h>
> #include <asm/hw_irq.h>
> +#include <asm/kvm_asm.h>
> +#include <asm/kvm_booke_hv_asm.h>
> 
> /* XXX This will ultimately add space for a special exception save
>  *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
> @@ -34,13 +36,24 @@
>  */
> #define	SPECIAL_EXC_FRAME_SIZE	INT_FRAME_SIZE
> 
> +#ifdef CONFIG_KVM_BOOKE_HV
> +#define KVM_BOOKE_HV_MFSPR(reg, spr)				\
> +	BEGIN_FTR_SECTION					\
> +		mfspr	reg, spr;			  	\
> +	END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
> +#else
> +#define KVM_BOOKE_HV_MFSPR(reg, spr)
> +#endif

Bleks - this is ugly. Do we really need to open-code the #ifdef here? Can't the feature section code determine that the feature is disabled and just always not include the code?

> +
> /* Exception prolog code for all exceptions */
> -#define EXCEPTION_PROLOG(n, type, srr0, srr1, addition)		     	    \
> +#define EXCEPTION_PROLOG(n, intnum, type, srr0, srr1, addition)		    \
> 	mtspr	SPRN_SPRG_##type##_SCRATCH,r13;	/* get spare registers */   \
> 	mfspr	r13,SPRN_SPRG_PACA;	/* get PACA */			    \
> 	std	r10,PACA_EX##type+EX_R10(r13);				    \
> 	std	r11,PACA_EX##type+EX_R11(r13);				    \
> 	mfcr	r10;			/* save CR */			    \
> +	KVM_BOOKE_HV_MFSPR(r11,srr1);			    		    \
> +	DO_KVM	intnum,srr1;				    		    \

So if DO_KVM already knows srr1, why explicitly do something with it the line above, and not in DO_KVM itself?

> 	addition;			/* additional code for that exc. */ \
> 	std	r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
> 	stw	r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
> @@ -69,17 +82,21 @@
> 	ld	r1,PACA_MC_STACK(r13);					    \
> 	subi	r1,r1,SPECIAL_EXC_FRAME_SIZE;
> 
> -#define NORMAL_EXCEPTION_PROLOG(n, addition)				    \
> -	EXCEPTION_PROLOG(n, GEN, SPRN_SRR0, SPRN_SRR1, addition##_GEN(n))
> +#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition)			    \
> +	EXCEPTION_PROLOG(n, intnum, GEN, SPRN_SRR0, SPRN_SRR1,		    \

We would we want to pass in 2 numbers? Let's please confine this onto a single ID per interrupt vector. Either we use the hardcoded ones available here in the KVM code or we use the KVM ones instead of the hardcoded ones here. But not both please. Just because it's like that on 32bit doesn't count as an excuse :).

> +					 addition##_GEN(n))
> 
> -#define CRIT_EXCEPTION_PROLOG(n, addition)				    \
> -	EXCEPTION_PROLOG(n, CRIT, SPRN_CSRR0, SPRN_CSRR1, addition##_CRIT(n))
> +#define CRIT_EXCEPTION_PROLOG(n, intnum, addition)			    \
> +	EXCEPTION_PROLOG(n, intnum, CRIT, SPRN_CSRR0, SPRN_CSRR1, 	    \
> +					 addition##_CRIT(n))
> 
> -#define DBG_EXCEPTION_PROLOG(n, addition)				    \
> -	EXCEPTION_PROLOG(n, DBG, SPRN_DSRR0, SPRN_DSRR1, addition##_DBG(n))
> +#define DBG_EXCEPTION_PROLOG(n, intnum, addition)			    \
> +	EXCEPTION_PROLOG(n, intnum, DBG, SPRN_DSRR0, SPRN_DSRR1, 	    \
> +					 addition##_DBG(n))
> 
> -#define MC_EXCEPTION_PROLOG(n, addition)				    \
> -	EXCEPTION_PROLOG(n, MC, SPRN_MCSRR0, SPRN_MCSRR1, addition##_MC(n))
> +#define MC_EXCEPTION_PROLOG(n, intnum, addition)			    \
> +	EXCEPTION_PROLOG(n, intnum, MC, SPRN_MCSRR0, SPRN_MCSRR1, 	    \
> +					 addition##_MC(n))
> 
> 
> /* Variants of the "addition" argument for the prolog
> @@ -226,9 +243,9 @@ exc_##n##_bad_stack:							    \
> 1:
> 
> 
> -#define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack)			\
> +#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack)		\
> 	START_EXCEPTION(label);						\
> -	NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE)	\
> +	NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
> 	EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE)		\
> 	ack(r8);							\
> 	CHECK_NAPPING();						\
> @@ -279,7 +296,8 @@ interrupt_end_book3e:
> 
> /* Critical Input Interrupt */
> 	START_EXCEPTION(critical_input);
> -	CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
> +	CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
> +			      PROLOG_ADDITION_NONE)
> //	EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE)
> //	bl	special_reg_save_crit
> //	CHECK_NAPPING();
> @@ -290,7 +308,8 @@ interrupt_end_book3e:
> 
> /* Machine Check Interrupt */
> 	START_EXCEPTION(machine_check);
> -	MC_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
> +	MC_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_MACHINE_CHECK,
> +			    PROLOG_ADDITION_NONE)
> //	EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE)
> //	bl	special_reg_save_mc
> //	addi	r3,r1,STACK_FRAME_OVERHEAD
> @@ -301,7 +320,8 @@ interrupt_end_book3e:
> 
> /* Data Storage Interrupt */
> 	START_EXCEPTION(data_storage)
> -	NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
> +	NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
> +				PROLOG_ADDITION_2REGS)
> 	mfspr	r14,SPRN_DEAR
> 	mfspr	r15,SPRN_ESR
> 	EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE)
> @@ -309,18 +329,21 @@ interrupt_end_book3e:
> 
> /* Instruction Storage Interrupt */
> 	START_EXCEPTION(instruction_storage);
> -	NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
> +	NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
> +				PROLOG_ADDITION_2REGS)
> 	li	r15,0
> 	mr	r14,r10
> 	EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE)
> 	b	storage_fault_common
> 
> /* External Input Interrupt */
> -	MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE)
> +	MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
> +			   external_input, .do_IRQ, ACK_NONE)
> 
> /* Alignment */
> 	START_EXCEPTION(alignment);
> -	NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS)
> +	NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
> +				PROLOG_ADDITION_2REGS)
> 	mfspr	r14,SPRN_DEAR
> 	mfspr	r15,SPRN_ESR
> 	EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
> @@ -328,7 +351,8 @@ interrupt_end_book3e:
> 
> /* Program Interrupt */
> 	START_EXCEPTION(program);
> -	NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
> +	NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
> +				PROLOG_ADDITION_1REG)
> 	mfspr	r14,SPRN_ESR
> 	EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE)
> 	std	r14,_DSISR(r1)
> @@ -340,7 +364,8 @@ interrupt_end_book3e:
> 
> /* Floating Point Unavailable Interrupt */
> 	START_EXCEPTION(fp_unavailable);
> -	NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
> +	NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
> +				PROLOG_ADDITION_NONE)
> 	/* we can probably do a shorter exception entry for that one... */
> 	EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
> 	ld	r12,_MSR(r1)
> @@ -355,14 +380,17 @@ interrupt_end_book3e:
> 	b	.ret_from_except
> 
> /* Decrementer Interrupt */
> -	MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
> +	MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
> +			   decrementer, .timer_interrupt, ACK_DEC)
> 
> /* Fixed Interval Timer Interrupt */
> -	MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT)
> +	MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
> +			   fixed_interval, .unknown_exception, ACK_FIT)
> 
> /* Watchdog Timer Interrupt */
> 	START_EXCEPTION(watchdog);
> -	CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
> +	CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
> +			      PROLOG_ADDITION_NONE)
> //	EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE)
> //	bl	special_reg_save_crit
> //	CHECK_NAPPING();
> @@ -381,7 +409,8 @@ interrupt_end_book3e:
> 
> /* Auxiliary Processor Unavailable Interrupt */
> 	START_EXCEPTION(ap_unavailable);
> -	NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
> +	NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
> +				PROLOG_ADDITION_NONE)
> 	EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE)
> 	bl	.save_nvgprs
> 	addi	r3,r1,STACK_FRAME_OVERHEAD
> @@ -390,7 +419,8 @@ interrupt_end_book3e:
> 
> /* Debug exception as a critical interrupt*/
> 	START_EXCEPTION(debug_crit);
> -	CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
> +	CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
> +			      PROLOG_ADDITION_2REGS)
> 
> 	/*
> 	 * If there is a single step or branch-taken exception in an
> @@ -455,7 +485,8 @@ kernel_dbg_exc:
> 
> /* Debug exception as a debug interrupt*/
> 	START_EXCEPTION(debug_debug);
> -	DBG_EXCEPTION_PROLOG(0xd08, PROLOG_ADDITION_2REGS)
> +	DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
> +						 PROLOG_ADDITION_2REGS)
> 
> 	/*
> 	 * If there is a single step or branch-taken exception in an
> @@ -516,18 +547,21 @@ kernel_dbg_exc:
> 	b	.ret_from_except
> 
> 	START_EXCEPTION(perfmon);
> -	NORMAL_EXCEPTION_PROLOG(0x260, PROLOG_ADDITION_NONE)
> +	NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
> +				PROLOG_ADDITION_NONE)
> 	EXCEPTION_COMMON(0x260, PACA_EXGEN, INTS_DISABLE)
> 	addi	r3,r1,STACK_FRAME_OVERHEAD
> 	bl	.performance_monitor_exception
> 	b	.ret_from_except_lite
> 
> /* Doorbell interrupt */
> -	MASKABLE_EXCEPTION(0x280, doorbell, .doorbell_exception, ACK_NONE)
> +	MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
> +			   doorbell, .doorbell_exception, ACK_NONE)
> 
> /* Doorbell critical Interrupt */
> 	START_EXCEPTION(doorbell_crit);
> -	CRIT_EXCEPTION_PROLOG(0x2a0, PROLOG_ADDITION_NONE)
> +	CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
> +			      PROLOG_ADDITION_NONE)
> //	EXCEPTION_COMMON(0x2a0, PACA_EXCRIT, INTS_DISABLE)
> //	bl	special_reg_save_crit
> //	CHECK_NAPPING();
> @@ -536,12 +570,24 @@ kernel_dbg_exc:
> //	b	ret_from_crit_except
> 	b	.
> 
> -/* Guest Doorbell */
> -	MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception, ACK_NONE)
> +/*
> + *	Guest doorbell interrupt
> + *	This general exception use GSRRx save/restore registers
> + */
> +	START_EXCEPTION(guest_doorbell);
> +	EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, GEN,
> +			 SPRN_GSRR0, SPRN_GSRR1, PROLOG_ADDITION_NONE)
> +	EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP)
> +	addi	r3,r1,STACK_FRAME_OVERHEAD
> +	bl	.save_nvgprs
> +	INTS_RESTORE_HARD
> +	bl	.unknown_exception
> +	b	.ret_from_except

This is independent of DO_KVM, right?

> 
> /* Guest Doorbell critical Interrupt */
> 	START_EXCEPTION(guest_doorbell_crit);
> -	CRIT_EXCEPTION_PROLOG(0x2e0, PROLOG_ADDITION_NONE)
> +	CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
> +			      PROLOG_ADDITION_NONE)

Shouldn't this one also use GSRR?

> //	EXCEPTION_COMMON(0x2e0, PACA_EXCRIT, INTS_DISABLE)
> //	bl	special_reg_save_crit
> //	CHECK_NAPPING();
> @@ -552,7 +598,8 @@ kernel_dbg_exc:
> 
> /* Hypervisor call */
> 	START_EXCEPTION(hypercall);
> -	NORMAL_EXCEPTION_PROLOG(0x310, PROLOG_ADDITION_NONE)
> +	NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
> +			        PROLOG_ADDITION_NONE)
> 	EXCEPTION_COMMON(0x310, PACA_EXGEN, INTS_KEEP)
> 	addi	r3,r1,STACK_FRAME_OVERHEAD
> 	bl	.save_nvgprs
> @@ -562,7 +609,8 @@ kernel_dbg_exc:
> 
> /* Embedded Hypervisor priviledged  */
> 	START_EXCEPTION(ehpriv);
> -	NORMAL_EXCEPTION_PROLOG(0x320, PROLOG_ADDITION_NONE)
> +	NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
> +			        PROLOG_ADDITION_NONE)
> 	EXCEPTION_COMMON(0x320, PACA_EXGEN, INTS_KEEP)
> 	addi	r3,r1,STACK_FRAME_OVERHEAD
> 	bl	.save_nvgprs
> diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
> index ff672bd..88feaaa 100644
> --- a/arch/powerpc/mm/tlb_low_64e.S
> +++ b/arch/powerpc/mm/tlb_low_64e.S
> @@ -20,6 +20,8 @@
> #include <asm/pgtable.h>
> #include <asm/exception-64e.h>
> #include <asm/ppc-opcode.h>
> +#include <asm/kvm_asm.h>
> +#include <asm/kvm_booke_hv_asm.h>
> 
> #ifdef CONFIG_PPC_64K_PAGES
> #define VPTE_PMD_SHIFT	(PTE_INDEX_SIZE+1)
> @@ -37,12 +39,18 @@
>  *                                                                    *
>  **********************************************************************/
> 
> -.macro tlb_prolog_bolted addr
> +.macro tlb_prolog_bolted intnum addr
> 	mtspr	SPRN_SPRG_TLB_SCRATCH,r13
> 	mfspr	r13,SPRN_SPRG_PACA
> 	std	r10,PACA_EXTLB+EX_TLB_R10(r13)
> 	mfcr	r10
> 	std	r11,PACA_EXTLB+EX_TLB_R11(r13)
> +#ifdef CONFIG_KVM_BOOKE_HV
> +BEGIN_FTR_SECTION
> +	mfspr	r11, SPRN_SRR1
> +END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
> +#endif

This thing really should vanish behind DO_KVM :)

Alex

> +	DO_KVM	\intnum, SPRN_SRR1
> 	std	r16,PACA_EXTLB+EX_TLB_R16(r13)
> 	mfspr	r16,\addr		/* get faulting address */
> 	std	r14,PACA_EXTLB+EX_TLB_R14(r13)
> @@ -66,7 +74,7 @@
> 
> /* Data TLB miss */
> 	START_EXCEPTION(data_tlb_miss_bolted)
> -	tlb_prolog_bolted SPRN_DEAR
> +	tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
> 
> 	/* We need _PAGE_PRESENT and  _PAGE_ACCESSED set */
> 
> @@ -214,7 +222,7 @@ itlb_miss_fault_bolted:
> 
> /* Instruction TLB miss */
> 	START_EXCEPTION(instruction_tlb_miss_bolted)
> -	tlb_prolog_bolted SPRN_SRR0
> +	tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
> 
> 	rldicl.	r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
> 	srdi	r15,r16,60		/* get region */
> -- 
> 1.7.4.1
> 
> 
> 

Re: [RFC PATCH 02/17] KVM: PPC64: booke: Add EPCR support in mtspr/mfspr emulation

[Alexander Graf]

On 04.07.2012, at 16:14, Caraman Mihai Claudiu-B02008 wrote:

>> -----Original Message-----
>> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
>> owner@vger.kernel.org] On Behalf Of Alexander Graf
>> Sent: Wednesday, July 04, 2012 4:22 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
>> Subject: Re: [RFC PATCH 02/17] KVM: PPC64: booke: Add EPCR support in
>> mtspr/mfspr emulation
>> 
>> 
>> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>> 
>>> Add EPCR support in booke mtspr/mfspr emulation. EPCR register is
>> defined
>>> only for 64-bit and HV categories, so it shoud be available only on 64-
>> bit
>>> virtual processors. Undefine the support for 32-bit builds.
>>> Define a reusable setter function for vcpu's EPCR.
>>> 
>>> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
>>> ---
>>> arch/powerpc/kvm/booke.c         |   12 +++++++++++-
>>> arch/powerpc/kvm/booke.h         |    6 ++++++
>>> arch/powerpc/kvm/booke_emulate.c |   13 ++++++++++++-
>>> 3 files changed, 29 insertions(+), 2 deletions(-)
>>> 
>>> diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
>>> index 72f13f4..f9fa260 100644
>>> --- a/arch/powerpc/kvm/booke.c
>>> +++ b/arch/powerpc/kvm/booke.c
>>> @@ -13,7 +13,7 @@
>>> * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
>> USA.
>>> *
>>> * Copyright IBM Corp. 2007
>>> - * Copyright 2010-2011 Freescale Semiconductor, Inc.
>>> + * Copyright 2010-2012 Freescale Semiconductor, Inc.
>>> *
>>> * Authors: Hollis Blanchard <hollisb@us.ibm.com>
>>> *          Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
>>> @@ -1243,6 +1243,16 @@ void kvmppc_core_commit_memory_region(struct kvm
>> *kvm,
>>> {
>>> }
>>> 
>>> +#ifdef CONFIG_64BIT
>>> +void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr)
>>> +{
>>> +	vcpu->arch.epcr = new_epcr;
>>> +	vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM;
>>> +	if (vcpu->arch.epcr  & SPRN_EPCR_ICM)
>>> +		vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM;
>> 
>> Why would the setter be #ifdef CONFIG_64BIT? EPCR exists on e500mc too,
>> no? Please only #ifdef the GICM bits out.
> 
> kvmppc_set_epcr deals with guest EPCR and EPCR does not exist on a virtual e500mc
> as detailed in patch's comment. All callers are also guarded by #ifdef CONFIG_64BIT,
> my assumption was that we will not support a virtual core with 64-bit category
> on a 32-bit host.

My main concern is that every #ifdef potentially breaks things without us knowing. So the less #ifdef's we have, the better off we are. The spec only says that we don't _have_ to implement EPCR for non-hv non-64bit systems. It doesn't forbid to do so, right?


Alex

Re: [Qemu-ppc] [RFC PATCH 15/17] KVM: PPC64: bookehv: Add support for interrupt handling

[Alexander Graf]

On 25.06.2012, at 14:26, Mihai Caraman wrote:

> Add bookehv interrupt handling support for 64-bit hosts. Change common stack
> layout to refer PPC_LR_STKOFF kernel constant. Dispatch the 64-bit execution
> flow to the existing kvm_handler_common asm macro. Update input register
> values documentation.
> Only the bolted version of TLB miss exception handlers is supported now.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
> arch/powerpc/include/asm/kvm_booke_hv_asm.h |   12 +++-
> arch/powerpc/kvm/bookehv_interrupts.S       |  120 +++++++++++++++++++++++++--
> 2 files changed, 122 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/kvm_booke_hv_asm.h b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
> index 30a600f..8be6f87 100644
> --- a/arch/powerpc/include/asm/kvm_booke_hv_asm.h
> +++ b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
> @@ -1,5 +1,5 @@
> /*
> - * Copyright 2010-2011 Freescale Semiconductor, Inc.
> + * Copyright 2010-2012 Freescale Semiconductor, Inc.
>  *
>  * This program is free software; you can redistribute it and/or modify
>  * it under the terms of the GNU General Public License, version 2, as
> @@ -17,6 +17,7 @@
>  * there are no exceptions for which we fall through directly to
>  * the normal host handler.
>  *
> + * 32-bit host
>  * Expected inputs (normal exceptions):
>  *   SCRATCH0 = saved r10
>  *   r10 = thread struct
> @@ -33,6 +34,15 @@
>  *   *(r8 + GPR9) = saved r9
>  *   *(r8 + GPR10) = saved r10 (r10 not yet clobbered)
>  *   *(r8 + GPR11) = saved r11
> + *
> + * 64-bit host
> + * Expected inputs (exception types GEN/DBG/CRIT/MC):
> + *  r13 = PACA_POINTER
> + *  r10 = saved CR
> + *  SPRN_SPRG_##type##_SCRATCH = saved r13
> + *  *(r13 + PACA_EX##type + EX_R10) = saved r10
> + *  *(r13 + PACA_EX##type + EX_R11) = saved r11
> + * Only the bolted version of TLB miss exception handlers is supported now.
>  */
> .macro DO_KVM intno srr1
> #ifdef CONFIG_KVM_BOOKE_HV
> diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S
> index dff8ed4..04097de 100644
> --- a/arch/powerpc/kvm/bookehv_interrupts.S
> +++ b/arch/powerpc/kvm/bookehv_interrupts.S
> @@ -12,10 +12,11 @@
>  * along with this program; if not, write to the Free Software
>  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
>  *
> - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
> + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
>  *
>  * Author: Varun Sethi <varun.sethi@freescale.com>
>  * Author: Scott Wood <scotwood@freescale.com>
> + * Author: Mihai Caraman <mihai.caraman@freescale.com>
>  *
>  * This file is derived from arch/powerpc/kvm/booke_interrupts.S
>  */
> @@ -30,7 +31,11 @@
> #include <asm/bitsperlong.h>
> #include <asm/thread_info.h>
> 
> +#ifdef CONFIG_64BIT
> +#include <asm/exception-64e.h>
> +#else
> #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
> +#endif
> 
> #define LONGBYTES		(BITS_PER_LONG / 8)
> 
> @@ -38,20 +43,21 @@
> #define VCPU_GUEST_SPRG(n)	(VCPU_GUEST_SPRGS + (n * LONGBYTES))
> 
> /* The host stack layout: */
> -#define HOST_R1         (0 * LONGBYTES) /* Implied by stwu. */
> -#define HOST_CALLEE_LR  (1 * LONGBYTES)
> -#define HOST_RUN        (2 * LONGBYTES) /* struct kvm_run */
> +#define HOST_R1         0 /* Implied by stwu. */
> +#define HOST_CALLEE_LR  PPC_LR_STKOFF
> +#define HOST_RUN        (HOST_CALLEE_LR + LONGBYTES)
> /*
>  * r2 is special: it holds 'current', and it made nonvolatile in the
>  * kernel with the -ffixed-r2 gcc option.
>  */
> -#define HOST_R2         (3 * LONGBYTES)
> -#define HOST_CR         (4 * LONGBYTES)
> -#define HOST_NV_GPRS    (5 * LONGBYTES)
> +#define HOST_R2         (HOST_RUN + LONGBYTES)
> +#define HOST_CR         (HOST_R2 + LONGBYTES)
> +#define HOST_NV_GPRS    (HOST_CR + LONGBYTES)
> #define HOST_NV_GPR(n)  (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
> #define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + LONGBYTES)
> #define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
> -#define HOST_STACK_LR   (HOST_STACK_SIZE + LONGBYTES) /* In caller stack frame. */
> +/* LR in caller stack frame. */
> +#define HOST_STACK_LR	(HOST_STACK_SIZE + PPC_LR_STKOFF)
> 
> #define NEED_EMU		0x00000001 /* emulation -- save nv regs */
> #define NEED_DEAR		0x00000002 /* save faulting DEAR */
> @@ -202,6 +208,102 @@
> 	b	kvmppc_resume_host
> .endm
> 
> +#ifdef CONFIG_64BIT
> +/*
> + * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
> + */
> +.macro kvm_handler intno scratch, paca_ex, ex_r10, ex_r11, srr0, srr1, flags
> + _GLOBAL(kvmppc_handler_\intno\()_\srr1)

Is this code so vastly different from the 32bit variant that they can't be the same with a few simple ifdef's here and there?


Alex

RE: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: Alexander Graf [mailto:agraf@suse.de]
> Sent: Wednesday, July 04, 2012 5:30 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: <kvm-ppc@vger.kernel.org>; KVM list; linuxppc-dev; qemu-
> ppc@nongnu.org List; Benjamin Herrenschmidt
> Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM
> kernel hooks
> 
> 
> On 25.06.2012, at 14:26, Mihai Caraman wrote:
> 
> > Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit
> booke
> > see head_fsl_booke.S file. Extend interrupt handlers' parameter list
> with
> > interrupt vector numbers to accomodate the macro. Rework Guest Doorbell
> > handler to use the proper GSRRx save/restore registers.
> > Only the bolted version of tlb miss handers is addressed now.
> >
> > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> > ---
> > arch/powerpc/kernel/exceptions-64e.S |  114 ++++++++++++++++++++++++---
> -------
> > arch/powerpc/mm/tlb_low_64e.S        |   14 +++-
> > 2 files changed, 92 insertions(+), 36 deletions(-)
> >
> > diff --git a/arch/powerpc/kernel/exceptions-64e.S
> b/arch/powerpc/kernel/exceptions-64e.S
> > index 06f7aec..a60f81f 100644
> > --- a/arch/powerpc/kernel/exceptions-64e.S
> > +++ b/arch/powerpc/kernel/exceptions-64e.S
> > @@ -25,6 +25,8 @@
> > #include <asm/ppc-opcode.h>
> > #include <asm/mmu.h>
> > #include <asm/hw_irq.h>
> > +#include <asm/kvm_asm.h>
> > +#include <asm/kvm_booke_hv_asm.h>
> >
> > /* XXX This will ultimately add space for a special exception save
> >  *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
> > @@ -34,13 +36,24 @@
> >  */
> > #define	SPECIAL_EXC_FRAME_SIZE	INT_FRAME_SIZE
> >
> > +#ifdef CONFIG_KVM_BOOKE_HV
> > +#define KVM_BOOKE_HV_MFSPR(reg, spr)				\
> > +	BEGIN_FTR_SECTION					\
> > +		mfspr	reg, spr;			  	\
> > +	END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
> > +#else
> > +#define KVM_BOOKE_HV_MFSPR(reg, spr)
> > +#endif
> 
> Bleks - this is ugly.

I agree :) But I opted to keep the optimizations done for 32-bit.

> Do we really need to open-code the #ifdef here?

32-bit implementation fortunately use asm macros, we can't nest defines.

> Can't the feature section code determine that the feature is disabled and
> just always not include the code?

CPU_FTR_EMB_HV is set even if KVM is not configured.

> 
> > +
> > /* Exception prolog code for all exceptions */
> > -#define EXCEPTION_PROLOG(n, type, srr0, srr1, addition)
> \
> > +#define EXCEPTION_PROLOG(n, intnum, type, srr0, srr1, addition)
> 	    \
> > 	mtspr	SPRN_SPRG_##type##_SCRATCH,r13;	/* get spare registers */
> \
> > 	mfspr	r13,SPRN_SPRG_PACA;	/* get PACA */			    \
> > 	std	r10,PACA_EX##type+EX_R10(r13);				    \
> > 	std	r11,PACA_EX##type+EX_R11(r13);				    \
> > 	mfcr	r10;			/* save CR */			    \
> > +	KVM_BOOKE_HV_MFSPR(r11,srr1);			    		    \
> > +	DO_KVM	intnum,srr1;				    		    \
> 
> So if DO_KVM already knows srr1, why explicitly do something with it the
> line above, and not in DO_KVM itself?

srr1 is used to expand the interrupt handler symbol name while r11 is used
for the actual MSR[GS] optimal check:
	mtocrf	0x80, r11

> > -/* Guest Doorbell */
> > -	MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception,
> ACK_NONE)
> > +/*
> > + *	Guest doorbell interrupt
> > + *	This general exception use GSRRx save/restore registers
> > + */
> > +	START_EXCEPTION(guest_doorbell);
> > +	EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, GEN,
> > +			 SPRN_GSRR0, SPRN_GSRR1, PROLOG_ADDITION_NONE)
> > +	EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP)
> > +	addi	r3,r1,STACK_FRAME_OVERHEAD
> > +	bl	.save_nvgprs
> > +	INTS_RESTORE_HARD
> > +	bl	.unknown_exception
> > +	b	.ret_from_except
> 
> This is independent of DO_KVM, right?

Yes, just kvm_handler definitions in bookehv_interrupts.S depends on this.

> 
> >
> > /* Guest Doorbell critical Interrupt */
> > 	START_EXCEPTION(guest_doorbell_crit);
> > -	CRIT_EXCEPTION_PROLOG(0x2e0, PROLOG_ADDITION_NONE)
> > +	CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
> > +			      PROLOG_ADDITION_NONE)
> 
> Shouldn't this one also use GSRR?

No, this is a critical exception.

> >
> > -.macro tlb_prolog_bolted addr
> > +.macro tlb_prolog_bolted intnum addr
> > 	mtspr	SPRN_SPRG_TLB_SCRATCH,r13
> > 	mfspr	r13,SPRN_SPRG_PACA
> > 	std	r10,PACA_EXTLB+EX_TLB_R10(r13)
> > 	mfcr	r10
> > 	std	r11,PACA_EXTLB+EX_TLB_R11(r13)
> > +#ifdef CONFIG_KVM_BOOKE_HV
> > +BEGIN_FTR_SECTION
> > +	mfspr	r11, SPRN_SRR1
> > +END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
> > +#endif
> 
> This thing really should vanish behind DO_KVM :)

Then let's do it first for 32-bit ;)

-Mike

RE: [Qemu-ppc] [RFC PATCH 15/17] KVM: PPC64: bookehv: Add support for interrupt handling

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
> owner@vger.kernel.org] On Behalf Of Alexander Graf
> Sent: Wednesday, July 04, 2012 6:14 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> Subject: Re: [Qemu-ppc] [RFC PATCH 15/17] KVM: PPC64: bookehv: Add
> support for interrupt handling
> 
> 
> On 25.06.2012, at 14:26, Mihai Caraman wrote:
> 
> > Add bookehv interrupt handling support for 64-bit hosts. Change common
> stack
> > layout to refer PPC_LR_STKOFF kernel constant. Dispatch the 64-bit
> execution
> > flow to the existing kvm_handler_common asm macro. Update input
> register
> > values documentation.
> > Only the bolted version of TLB miss exception handlers is supported
> now.
> >
> > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> > ---
> > arch/powerpc/include/asm/kvm_booke_hv_asm.h |   12 +++-
> > arch/powerpc/kvm/bookehv_interrupts.S       |  120
> +++++++++++++++++++++++++--
> > 2 files changed, 122 insertions(+), 10 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/kvm_booke_hv_asm.h
> b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
> > index 30a600f..8be6f87 100644
> > --- a/arch/powerpc/include/asm/kvm_booke_hv_asm.h
> > +++ b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
> > @@ -1,5 +1,5 @@
> > /*
> > - * Copyright 2010-2011 Freescale Semiconductor, Inc.
> > + * Copyright 2010-2012 Freescale Semiconductor, Inc.
> >  *
> >  * This program is free software; you can redistribute it and/or modify
> >  * it under the terms of the GNU General Public License, version 2, as
> > @@ -17,6 +17,7 @@
> >  * there are no exceptions for which we fall through directly to
> >  * the normal host handler.
> >  *
> > + * 32-bit host
> >  * Expected inputs (normal exceptions):
> >  *   SCRATCH0 = saved r10
> >  *   r10 = thread struct
> > @@ -33,6 +34,15 @@
> >  *   *(r8 + GPR9) = saved r9
> >  *   *(r8 + GPR10) = saved r10 (r10 not yet clobbered)
> >  *   *(r8 + GPR11) = saved r11
> > + *
> > + * 64-bit host
> > + * Expected inputs (exception types GEN/DBG/CRIT/MC):
> > + *  r13 = PACA_POINTER
> > + *  r10 = saved CR
> > + *  SPRN_SPRG_##type##_SCRATCH = saved r13
> > + *  *(r13 + PACA_EX##type + EX_R10) = saved r10
> > + *  *(r13 + PACA_EX##type + EX_R11) = saved r11
> > + * Only the bolted version of TLB miss exception handlers is supported
> now.
> >  */
> > .macro DO_KVM intno srr1
> > #ifdef CONFIG_KVM_BOOKE_HV
> > diff --git a/arch/powerpc/kvm/bookehv_interrupts.S
> b/arch/powerpc/kvm/bookehv_interrupts.S
> > index dff8ed4..04097de 100644
> > --- a/arch/powerpc/kvm/bookehv_interrupts.S
> > +++ b/arch/powerpc/kvm/bookehv_interrupts.S
> > @@ -12,10 +12,11 @@
> >  * along with this program; if not, write to the Free Software
> >  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
> USA.
> >  *
> > - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
> > + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
> >  *
> >  * Author: Varun Sethi <varun.sethi@freescale.com>
> >  * Author: Scott Wood <scotwood@freescale.com>
> > + * Author: Mihai Caraman <mihai.caraman@freescale.com>
> >  *
> >  * This file is derived from arch/powerpc/kvm/booke_interrupts.S
> >  */
> > @@ -30,7 +31,11 @@
> > #include <asm/bitsperlong.h>
> > #include <asm/thread_info.h>
> >
> > +#ifdef CONFIG_64BIT
> > +#include <asm/exception-64e.h>
> > +#else
> > #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
> > +#endif
> >
> >
> > +#ifdef CONFIG_64BIT
> > +/*
> > + * For input register values, see
> arch/powerpc/include/asm/kvm_booke_hv_asm.h
> > + */
> > +.macro kvm_handler intno scratch, paca_ex, ex_r10, ex_r11, srr0, srr1,
> flags
> > + _GLOBAL(kvmppc_handler_\intno\()_\srr1)
> 
> Is this code so vastly different from the 32bit variant that they can't
> be the same with a few simple ifdef's here and there?

As you can see from input register values things are quite different. I strived
to keep the code common, the only divergence is in the kvm_handler definitions.

-Mike

Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Alexander Graf]

On 04.07.2012, at 17:27, Caraman Mihai Claudiu-B02008 wrote:

>> -----Original Message-----
>> From: Alexander Graf [mailto:agraf@suse.de]
>> Sent: Wednesday, July 04, 2012 5:30 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: <kvm-ppc@vger.kernel.org>; KVM list; linuxppc-dev; qemu-
>> ppc@nongnu.org List; Benjamin Herrenschmidt
>> Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM
>> kernel hooks
>> 
>> 
>> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>> 
>>> Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit
>> booke
>>> see head_fsl_booke.S file. Extend interrupt handlers' parameter list
>> with
>>> interrupt vector numbers to accomodate the macro. Rework Guest Doorbell
>>> handler to use the proper GSRRx save/restore registers.
>>> Only the bolted version of tlb miss handers is addressed now.
>>> 
>>> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
>>> ---
>>> arch/powerpc/kernel/exceptions-64e.S |  114 ++++++++++++++++++++++++---
>> -------
>>> arch/powerpc/mm/tlb_low_64e.S        |   14 +++-
>>> 2 files changed, 92 insertions(+), 36 deletions(-)
>>> 
>>> diff --git a/arch/powerpc/kernel/exceptions-64e.S
>> b/arch/powerpc/kernel/exceptions-64e.S
>>> index 06f7aec..a60f81f 100644
>>> --- a/arch/powerpc/kernel/exceptions-64e.S
>>> +++ b/arch/powerpc/kernel/exceptions-64e.S
>>> @@ -25,6 +25,8 @@
>>> #include <asm/ppc-opcode.h>
>>> #include <asm/mmu.h>
>>> #include <asm/hw_irq.h>
>>> +#include <asm/kvm_asm.h>
>>> +#include <asm/kvm_booke_hv_asm.h>
>>> 
>>> /* XXX This will ultimately add space for a special exception save
>>> *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
>>> @@ -34,13 +36,24 @@
>>> */
>>> #define	SPECIAL_EXC_FRAME_SIZE	INT_FRAME_SIZE
>>> 
>>> +#ifdef CONFIG_KVM_BOOKE_HV
>>> +#define KVM_BOOKE_HV_MFSPR(reg, spr)				\
>>> +	BEGIN_FTR_SECTION					\
>>> +		mfspr	reg, spr;			  	\
>>> +	END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
>>> +#else
>>> +#define KVM_BOOKE_HV_MFSPR(reg, spr)
>>> +#endif
>> 
>> Bleks - this is ugly.
> 
> I agree :) But I opted to keep the optimizations done for 32-bit.
> 
>> Do we really need to open-code the #ifdef here?
> 
> 32-bit implementation fortunately use asm macros, we can't nest defines.
> 
>> Can't the feature section code determine that the feature is disabled and
>> just always not include the code?
> 
> CPU_FTR_EMB_HV is set even if KVM is not configured.

I don't get the point then. Why not have the whole DO_KVM masked under FTR_SECTION_IFSET(CPU_FTR_EMB_HV)? Are there book3s_64 implementations without HV? Can't we just mfspr unconditionally in DO_KVM?

> 
>> 
>>> +
>>> /* Exception prolog code for all exceptions */
>>> -#define EXCEPTION_PROLOG(n, type, srr0, srr1, addition)
>> \
>>> +#define EXCEPTION_PROLOG(n, intnum, type, srr0, srr1, addition)
>> 	    \
>>> 	mtspr	SPRN_SPRG_##type##_SCRATCH,r13;	/* get spare registers */
>> \
>>> 	mfspr	r13,SPRN_SPRG_PACA;	/* get PACA */			    \
>>> 	std	r10,PACA_EX##type+EX_R10(r13);				    \
>>> 	std	r11,PACA_EX##type+EX_R11(r13);				    \
>>> 	mfcr	r10;			/* save CR */			    \
>>> +	KVM_BOOKE_HV_MFSPR(r11,srr1);			    		    \
>>> +	DO_KVM	intnum,srr1;				    		    \
>> 
>> So if DO_KVM already knows srr1, why explicitly do something with it the
>> line above, and not in DO_KVM itself?
> 
> srr1 is used to expand the interrupt handler symbol name while r11 is used
> for the actual MSR[GS] optimal check:
> 	mtocrf	0x80, r11

Right, so basically we want

#ifdef CONFIG_KVM
mfspr r11, spr
mtocrf 0x80, r11
beq ...
#endif

right?

> 
>>> -/* Guest Doorbell */
>>> -	MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception,
>> ACK_NONE)
>>> +/*
>>> + *	Guest doorbell interrupt
>>> + *	This general exception use GSRRx save/restore registers
>>> + */
>>> +	START_EXCEPTION(guest_doorbell);
>>> +	EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, GEN,
>>> +			 SPRN_GSRR0, SPRN_GSRR1, PROLOG_ADDITION_NONE)
>>> +	EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP)
>>> +	addi	r3,r1,STACK_FRAME_OVERHEAD
>>> +	bl	.save_nvgprs
>>> +	INTS_RESTORE_HARD
>>> +	bl	.unknown_exception
>>> +	b	.ret_from_except
>> 
>> This is independent of DO_KVM, right?
> 
> Yes, just kvm_handler definitions in bookehv_interrupts.S depends on this.

Then please split it out into a separate patch.

> 
>> 
>>> 
>>> /* Guest Doorbell critical Interrupt */
>>> 	START_EXCEPTION(guest_doorbell_crit);
>>> -	CRIT_EXCEPTION_PROLOG(0x2e0, PROLOG_ADDITION_NONE)
>>> +	CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
>>> +			      PROLOG_ADDITION_NONE)
>> 
>> Shouldn't this one also use GSRR?
> 
> No, this is a critical exception.

Ah, right. Looked at the wrong bit, sorry :).

> 
>>> 
>>> -.macro tlb_prolog_bolted addr
>>> +.macro tlb_prolog_bolted intnum addr
>>> 	mtspr	SPRN_SPRG_TLB_SCRATCH,r13
>>> 	mfspr	r13,SPRN_SPRG_PACA
>>> 	std	r10,PACA_EXTLB+EX_TLB_R10(r13)
>>> 	mfcr	r10
>>> 	std	r11,PACA_EXTLB+EX_TLB_R11(r13)
>>> +#ifdef CONFIG_KVM_BOOKE_HV
>>> +BEGIN_FTR_SECTION
>>> +	mfspr	r11, SPRN_SRR1
>>> +END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
>>> +#endif
>> 
>> This thing really should vanish behind DO_KVM :)
> 
> Then let's do it first for 32-bit ;)

You could #ifdef it in DO_KVM for 64-bit for now. IIRC it's not done on 32-bit because the register value is used even beyond DO_KVM there.


Alex

Re: [Qemu-ppc] [RFC PATCH 15/17] KVM: PPC64: bookehv: Add support for interrupt handling

[Alexander Graf]

On 04.07.2012, at 17:37, Caraman Mihai Claudiu-B02008 wrote:

>> -----Original Message-----
>> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
>> owner@vger.kernel.org] On Behalf Of Alexander Graf
>> Sent: Wednesday, July 04, 2012 6:14 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
>> Subject: Re: [Qemu-ppc] [RFC PATCH 15/17] KVM: PPC64: bookehv: Add
>> support for interrupt handling
>> 
>> 
>> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>> 
>>> Add bookehv interrupt handling support for 64-bit hosts. Change common
>> stack
>>> layout to refer PPC_LR_STKOFF kernel constant. Dispatch the 64-bit
>> execution
>>> flow to the existing kvm_handler_common asm macro. Update input
>> register
>>> values documentation.
>>> Only the bolted version of TLB miss exception handlers is supported
>> now.
>>> 
>>> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
>>> ---
>>> arch/powerpc/include/asm/kvm_booke_hv_asm.h |   12 +++-
>>> arch/powerpc/kvm/bookehv_interrupts.S       |  120
>> +++++++++++++++++++++++++--
>>> 2 files changed, 122 insertions(+), 10 deletions(-)
>>> 
>>> diff --git a/arch/powerpc/include/asm/kvm_booke_hv_asm.h
>> b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
>>> index 30a600f..8be6f87 100644
>>> --- a/arch/powerpc/include/asm/kvm_booke_hv_asm.h
>>> +++ b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
>>> @@ -1,5 +1,5 @@
>>> /*
>>> - * Copyright 2010-2011 Freescale Semiconductor, Inc.
>>> + * Copyright 2010-2012 Freescale Semiconductor, Inc.
>>> *
>>> * This program is free software; you can redistribute it and/or modify
>>> * it under the terms of the GNU General Public License, version 2, as
>>> @@ -17,6 +17,7 @@
>>> * there are no exceptions for which we fall through directly to
>>> * the normal host handler.
>>> *
>>> + * 32-bit host
>>> * Expected inputs (normal exceptions):
>>> *   SCRATCH0 = saved r10
>>> *   r10 = thread struct
>>> @@ -33,6 +34,15 @@
>>> *   *(r8 + GPR9) = saved r9
>>> *   *(r8 + GPR10) = saved r10 (r10 not yet clobbered)
>>> *   *(r8 + GPR11) = saved r11
>>> + *
>>> + * 64-bit host
>>> + * Expected inputs (exception types GEN/DBG/CRIT/MC):
>>> + *  r13 = PACA_POINTER
>>> + *  r10 = saved CR
>>> + *  SPRN_SPRG_##type##_SCRATCH = saved r13
>>> + *  *(r13 + PACA_EX##type + EX_R10) = saved r10
>>> + *  *(r13 + PACA_EX##type + EX_R11) = saved r11
>>> + * Only the bolted version of TLB miss exception handlers is supported
>> now.
>>> */
>>> .macro DO_KVM intno srr1
>>> #ifdef CONFIG_KVM_BOOKE_HV
>>> diff --git a/arch/powerpc/kvm/bookehv_interrupts.S
>> b/arch/powerpc/kvm/bookehv_interrupts.S
>>> index dff8ed4..04097de 100644
>>> --- a/arch/powerpc/kvm/bookehv_interrupts.S
>>> +++ b/arch/powerpc/kvm/bookehv_interrupts.S
>>> @@ -12,10 +12,11 @@
>>> * along with this program; if not, write to the Free Software
>>> * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
>> USA.
>>> *
>>> - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
>>> + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
>>> *
>>> * Author: Varun Sethi <varun.sethi@freescale.com>
>>> * Author: Scott Wood <scotwood@freescale.com>
>>> + * Author: Mihai Caraman <mihai.caraman@freescale.com>
>>> *
>>> * This file is derived from arch/powerpc/kvm/booke_interrupts.S
>>> */
>>> @@ -30,7 +31,11 @@
>>> #include <asm/bitsperlong.h>
>>> #include <asm/thread_info.h>
>>> 
>>> +#ifdef CONFIG_64BIT
>>> +#include <asm/exception-64e.h>
>>> +#else
>>> #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
>>> +#endif
>>> 
>>> 
>>> +#ifdef CONFIG_64BIT
>>> +/*
>>> + * For input register values, see
>> arch/powerpc/include/asm/kvm_booke_hv_asm.h
>>> + */
>>> +.macro kvm_handler intno scratch, paca_ex, ex_r10, ex_r11, srr0, srr1,
>> flags
>>> + _GLOBAL(kvmppc_handler_\intno\()_\srr1)
>> 
>> Is this code so vastly different from the 32bit variant that they can't
>> be the same with a few simple ifdef's here and there?
> 
> As you can see from input register values things are quite different. I strived
> to keep the code common, the only divergence is in the kvm_handler definitions.

What a shame :(. A lot of it looks very very similar.


Alex

RE: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Caraman Mihai Claudiu-B02008]

>________________________________________
>From: Alexander Graf [agraf@suse.de]
>Sent: Wednesday, July 04, 2012 6:45 PM
>To: Caraman Mihai Claudiu-B02008
>Cc: <kvm-ppc@vger.kernel.org>; KVM list; linuxppc-dev; qemu-ppc@nongnu.org List; Benjamin Herrenschmidt
>Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks
>
>On 04.07.2012, at 17:27, Caraman Mihai Claudiu-B02008 wrote:
>
>>> -----Original Message-----
>>> From: Alexander Graf [mailto:agraf@suse.de]
>>> Sent: Wednesday, July 04, 2012 5:30 PM
>>> To: Caraman Mihai Claudiu-B02008
>>> Cc: <kvm-ppc@vger.kernel.org>; KVM list; linuxppc-dev; qemu-
>>> ppc@nongnu.org List; Benjamin Herrenschmidt
>>> Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM
>>> kernel hooks
>>>
>>>
>>> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>>>
>>>> Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit
>>> booke
>>>> see head_fsl_booke.S file. Extend interrupt handlers' parameter list
>>> with
>>>> interrupt vector numbers to accomodate the macro. Rework Guest Doorbell
>>>> handler to use the proper GSRRx save/restore registers.
>>>> Only the bolted version of tlb miss handers is addressed now.
>>>>
>>>> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
>>>> ---
>>>> arch/powerpc/kernel/exceptions-64e.S |  114 ++++++++++++++++++++++++---
>>> -------
>>>> arch/powerpc/mm/tlb_low_64e.S        |   14 +++-
>>>> 2 files changed, 92 insertions(+), 36 deletions(-)
>>>>
>>>> diff --git a/arch/powerpc/kernel/exceptions-64e.S
>>> b/arch/powerpc/kernel/exceptions-64e.S
>>>> index 06f7aec..a60f81f 100644
>>>> --- a/arch/powerpc/kernel/exceptions-64e.S
>>>> +++ b/arch/powerpc/kernel/exceptions-64e.S
>>>> @@ -25,6 +25,8 @@
>>>> #include <asm/ppc-opcode.h>
>>>> #include <asm/mmu.h>
>>>> #include <asm/hw_irq.h>
>>>> +#include <asm/kvm_asm.h>
>>>> +#include <asm/kvm_booke_hv_asm.h>
>>>>
>>>> /* XXX This will ultimately add space for a special exception save
>>>> *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
>>>> @@ -34,13 +36,24 @@
>>>> */
>>>> #define     SPECIAL_EXC_FRAME_SIZE  INT_FRAME_SIZE
>>>>
>>>> +#ifdef CONFIG_KVM_BOOKE_HV
>>>> +#define KVM_BOOKE_HV_MFSPR(reg, spr)                               \
>>>> +   BEGIN_FTR_SECTION                                       \
>>>> +           mfspr   reg, spr;                               \
>>>> +   END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
>>>> +#else
>>>> +#define KVM_BOOKE_HV_MFSPR(reg, spr)
>>>> +#endif
>>>
>>> Bleks - this is ugly.
>>
>> I agree :) But I opted to keep the optimizations done for 32-bit.
>>
>>> Do we really need to open-code the #ifdef here?
>>
>> 32-bit implementation fortunately use asm macros, we can't nest defines.
>>
>>> Can't the feature section code determine that the feature is disabled and
>>> just always not include the code?
>>
>> CPU_FTR_EMB_HV is set even if KVM is not configured.
>
>I don't get the point then. Why not have the whole DO_KVM masked under FTR_SECTION_IFSET(CPU_FTR_EMB_HV)? Are there book3s_64 implementations without HV? 

I guess you refer to book3e_64. I don't know all implementations but Embedded.HV category is optional.

>Can't we just mfspr unconditionally in DO_KVM?

I think Scott should better answer this question, I don't know why he opted for the other approach.

>>>> -/* Guest Doorbell */
>>>> -   MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception,
>>> ACK_NONE)
>>>> +/*
>>>> + * Guest doorbell interrupt
>>>> + * This general exception use GSRRx save/restore registers
>>>> + */
>>>> +   START_EXCEPTION(guest_doorbell);
>>>> +   EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, GEN,
>>>> +                    SPRN_GSRR0, SPRN_GSRR1, PROLOG_ADDITION_NONE)
>>>> +   EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP)
>>>> +   addi    r3,r1,STACK_FRAME_OVERHEAD
>>>> +   bl      .save_nvgprs
>>>> +   INTS_RESTORE_HARD
>>>> +   bl      .unknown_exception
>>>> +   b       .ret_from_except
>>>
>>> This is independent of DO_KVM, right?
>>
>> Yes, just kvm_handler definitions in bookehv_interrupts.S depends on this.
>
>Then please split it out into a separate patch.

Can you be more precise, are you referring to guest_doorbell exception handler?

>>>> -.macro tlb_prolog_bolted addr
>>>> +.macro tlb_prolog_bolted intnum addr
>>>>     mtspr   SPRN_SPRG_TLB_SCRATCH,r13
>>>>     mfspr   r13,SPRN_SPRG_PACA
>>>>     std     r10,PACA_EXTLB+EX_TLB_R10(r13)
>>>>     mfcr    r10
>>>>     std     r11,PACA_EXTLB+EX_TLB_R11(r13)
>>>> +#ifdef CONFIG_KVM_BOOKE_HV
>>>> +BEGIN_FTR_SECTION
>>>> +   mfspr   r11, SPRN_SRR1
>>>> +END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
>>>> +#endif
>>>
>>> This thing really should vanish behind DO_KVM :)
>>
>> Then let's do it first for 32-bit ;)
>
>You could #ifdef it in DO_KVM for 64-bit for now. IIRC it's not done on 32-bit because the register value is used even beyond DO_KVM there.

Nope, 32-bit code is also guarded by CONFIG_KVM_BOOKE_HV.

-Mike

RE: [Qemu-ppc] [RFC PATCH 15/17] KVM: PPC64: bookehv: Add support for interrupt handling

[Caraman Mihai Claudiu-B02008]

>On 04.07.2012, at 17:37, Caraman Mihai Claudiu-B02008 wrote:
>
>>> -----Original Message-----
>>> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
>>> owner@vger.kernel.org] On Behalf Of Alexander Graf
>>> Sent: Wednesday, July 04, 2012 6:14 PM
>>> To: Caraman Mihai Claudiu-B02008
>>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>>> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
>>> Subject: Re: [Qemu-ppc] [RFC PATCH 15/17] KVM: PPC64: bookehv: Add
>>> support for interrupt handling
>>>
>>> Is this code so vastly different from the 32bit variant that they can't
>>> be the same with a few simple ifdef's here and there?
>>
>> As you can see from input register values things are quite different. I strived
>> to keep the code common, the only divergence is in the kvm_handler definitions.
>
>What a shame :(. A lot of it looks very very similar.

The Devil is in the details ;)

-Mike

Re: [Qemu-ppc] [RFC PATCH 09/17] KVM: PPC64: booke: Hard disable interrupts when entering guest

[Benjamin Herrenschmidt]

On Wed, 2012-07-04 at 16:14 +0200, Alexander Graf wrote:
> > +#ifdef CONFIG_64BIT
> > +#define _hard_irq_disable() hard_irq_disable()
> > +#else
> > +#define _hard_irq_disable() local_irq_disable()
> > +#endif
> 
> So you only swap out the disable bit, but not the enable one? Ben,
> would this work out?

hard_irq_disable() both soft and hard disable. local_irq_enable() will
see that irqs are hard disabled and will hard enable.

However, there's a nastier discrepancy above: local_irq_disable will
properly inform lockdep that we are disabling, while hard_irq_disable
won't.

Arguably we might want to fix that inside hard_irq_disable() itself...

Also you need to be careful. If you are coming with interrupts already
enabled, it's fine, but if you have interrupts soft disabled, then
you hard disable, before you enter the guest you probably want to
check if anything was left "pending" and cancel the entering of the
guest if that is the case.

Cheers,
Ben.

Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Benjamin Herrenschmidt]

On Wed, 2012-07-04 at 16:29 +0200, Alexander Graf wrote:
 
> > +#ifdef CONFIG_KVM_BOOKE_HV
> > +#define KVM_BOOKE_HV_MFSPR(reg, spr)				\
> > +	BEGIN_FTR_SECTION					\
> > +		mfspr	reg, spr;			  	\
> > +	END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
> > +#else
> > +#define KVM_BOOKE_HV_MFSPR(reg, spr)
> > +#endif
> 
> Bleks - this is ugly. Do we really need to open-code the #ifdef here?
> Can't the feature section code determine that the feature is disabled
> and just always not include the code?

You can't but in any case I don't see the point of the conditional here,
we'll eventually have to load srr1 no ? We can move the load up to here
in all cases or can't we ? If really not, we could have it inside DO_KVM
and be done with it no ?

> > +
> > /* Exception prolog code for all exceptions */
> > -#define EXCEPTION_PROLOG(n, type, srr0, srr1, addition)		     	    \
> > +#define EXCEPTION_PROLOG(n, intnum, type, srr0, srr1, addition)		    \
> > 	mtspr	SPRN_SPRG_##type##_SCRATCH,r13;	/* get spare registers */   \
> > 	mfspr	r13,SPRN_SPRG_PACA;	/* get PACA */			    \
> > 	std	r10,PACA_EX##type+EX_R10(r13);				    \
> > 	std	r11,PACA_EX##type+EX_R11(r13);				    \
> > 	mfcr	r10;			/* save CR */			    \
> > +	KVM_BOOKE_HV_MFSPR(r11,srr1);			    		    \
> > +	DO_KVM	intnum,srr1;				    		    \
> 
> So if DO_KVM already knows srr1, why explicitly do something with it
> the line above, and not in DO_KVM itself?

Yeah that or just move things around in the prolog.

> > 	addition;			/* additional code for that exc. */ \
> > 	std	r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
> > 	stw	r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
> > @@ -69,17 +82,21 @@
> > 	ld	r1,PACA_MC_STACK(r13);					    \
> > 	subi	r1,r1,SPECIAL_EXC_FRAME_SIZE;
> > 
> > -#define NORMAL_EXCEPTION_PROLOG(n, addition)				    \
> > -	EXCEPTION_PROLOG(n, GEN, SPRN_SRR0, SPRN_SRR1, addition##_GEN(n))
> > +#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition)			    \
> > +	EXCEPTION_PROLOG(n, intnum, GEN, SPRN_SRR0, SPRN_SRR1,		    \
> 
> We would we want to pass in 2 numbers? Let's please confine this onto
> a single ID per interrupt vector. Either we use the hardcoded ones
> available here in the KVM code or we use the KVM ones instead of the
> hardcoded ones here. But not both please. Just because it's like that
> on 32bit doesn't count as an excuse :).

Right. Also I already objected to the explicit passing of the srr's
anyway.

Cheers,
Ben.

RE: [Qemu-ppc] [RFC PATCH 04/17] KVM: PPC64: booke: Add guest computation mode for irq delivery

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: Alexander Graf [mailto:agraf@suse.de]
> Sent: Wednesday, July 04, 2012 4:41 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> Subject: Re: [Qemu-ppc] [RFC PATCH 04/17] KVM: PPC64: booke: Add guest
> computation mode for irq delivery
> 
> 
> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>
> > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> > ---
> > arch/powerpc/kvm/booke.c |    8 +++++++-
> > 1 files changed, 7 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
> > index d15c4b5..93b48e0 100644
> > --- a/arch/powerpc/kvm/booke.c
> > +++ b/arch/powerpc/kvm/booke.c
> > @@ -287,6 +287,7 @@ static int kvmppc_booke_irqprio_deliver(struct
> kvm_vcpu *vcpu,
> > 	bool crit;
> > 	bool keep_irq = false;
> > 	enum int_class int_class;
> > +	ulong msr_cm = 0;
> >
> > 	/* Truncate crit indicators in 32 bit mode */
> > 	if (!(vcpu->arch.shared->msr & MSR_SF)) {
> > @@ -299,6 +300,10 @@ static int kvmppc_booke_irqprio_deliver(struct
> kvm_vcpu *vcpu,
> > 	/* ... and we're in supervisor mode */
> > 	crit = crit && !(vcpu->arch.shared->msr & MSR_PR);
> >
> > +#ifdef CONFIG_64BIT
> > +	msr_cm = vcpu->arch.epcr & SPRN_EPCR_ICM ? MSR_CM : 0;
> > +#endif
> 
> No need for the ifdef, no?. Just mask EPCR_ICM out in the 32-bit host
> case, then this check is always false on 32-bit hosts.

It will break e500v2. epcr field is declared only for CONFIG_KVM_BOOKE_HV,
we can limit to this instead of CONFIG_64BIT.

-Mike

RE: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2 EPN mask for 64-bit

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: Alexander Graf [mailto:agraf@suse.de]
> Sent: Wednesday, July 04, 2012 4:50 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2
> EPN mask for 64-bit
> 
> 
> On 25.06.2012, at 14:26, Mihai Caraman wrote:
> 
> > Extend MAS2 EPN mask for 64-bit hosts, to retain most significant bits.
> > Change get tlb eaddr to use this mask.
> 
> Please see section 6.11.4.8 in the PowerISA 2.06b:
> 
> MMU behavior is largely unaffected by whether the thread is in 32-bit
> computation mode (MSRCM=0) or 64- bit computation mode (MSRCM=1). The
> only differ- ences occur in the EPN field of the TLB entry and the EPN
> field of MAS2. The differences are summarized here.
> 
> 	*  Executing a tlbwe instruction in 32-bit mode will set bits 0:31
> of the TLB EPN field to zero unless MAS0ATSEL is set, in which case those
> bits are not written to zero.
> 	*  In 32-bit implementations, MAS2U can be used to read or write
> EPN0:31 of MAS2.
> 
> So if MSR.CM is not set tlbwe should mask the upper 32 bits out - which
> can happen regardless of CONFIG_64BIT.

MAS2_EPN reflects EPN field of MAS2 aka bits 0:51 (for MAV = 1.0) according
to section 6.10.3.10 in the PowerISA 2.06b.

MAS2_EPN is not used in tlbwe execution emulation, we have MAS2_VAL define
for this case.

> Also, we need to implement MAS2U, to potentially make the upper 32bits of
> MAS2 available, right? But that one isn't as important as the first bit.

MAS2U is guest privileged why does it need special care?

Freescale core Manuals and EREF does not mention MAS2U so I think I our case
it is not implemented.

-Mike

RE: [RFC PATCH 06/17] KVM: PPC: e500: Add emulation helper for getting instruction ea

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
> owner@vger.kernel.org] On Behalf Of Alexander Graf
> Sent: Wednesday, July 04, 2012 4:56 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> Subject: Re: [RFC PATCH 06/17] KVM: PPC: e500: Add emulation helper for
> getting instruction ea
> 
> 
> On 25.06.2012, at 14:26, Mihai Caraman wrote:
> 
> > Add emulation helper for getting instruction ea and refactor tlb
> instruction
> > emulation to use it.
> >
> > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> > ---
> > arch/powerpc/kvm/e500.h         |    6 +++---
> > arch/powerpc/kvm/e500_emulate.c |   21 ++++++++++++++++++---
> > arch/powerpc/kvm/e500_tlb.c     |   23 ++++++-----------------
> > 3 files changed, 27 insertions(+), 23 deletions(-)
> >
> > diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
> > index 3e31098..70bfed4 100644
> > --- a/arch/powerpc/kvm/e500.h
> > +++ b/arch/powerpc/kvm/e500.h
> > @@ -130,9 +130,9 @@ int kvmppc_e500_emul_mt_mmucsr0(struct
> kvmppc_vcpu_e500 *vcpu_e500,
> > 				ulong value);
> > int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu);
> > int kvmppc_e500_emul_tlbre(struct kvm_vcpu *vcpu);
> > -int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, int ra, int rb);
> > -int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, int ra, int
> rb);
> > -int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, int rb);
> > +int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, gva_t ea);
> > +int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, gva_t ea);
> > +int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, gva_t ea);
> > int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 *vcpu_e500);
> > void kvmppc_e500_tlb_uninit(struct kvmppc_vcpu_e500 *vcpu_e500);
> >
> > diff --git a/arch/powerpc/kvm/e500_emulate.c
> b/arch/powerpc/kvm/e500_emulate.c
> > index 8b99e07..81288f7 100644
> > --- a/arch/powerpc/kvm/e500_emulate.c
> > +++ b/arch/powerpc/kvm/e500_emulate.c
> > @@ -82,6 +82,17 @@ static int kvmppc_e500_emul_msgsnd(struct kvm_vcpu
> *vcpu, int rb)
> > }
> > #endif
> >
> > +static inline ulong kvmppc_get_ea_indexed(struct kvm_vcpu *vcpu, int
> ra, int rb)
> > +{
> > +	ulong ea;
> > +
> > +	ea = kvmppc_get_gpr(vcpu, rb);
> > +	if (ra)
> > +		ea += kvmppc_get_gpr(vcpu, ra);
> > +
> > +	return ea;
> > +}
> > +
> 
> Please move this one to arch/powerpc/include/asm/kvm_ppc.h.

Yep. This is similar with what I had in my internal version before emulation
refactoring took place upstream. The only difference is that I split the embedded
and server implementation touching this files:
	arch/powerpc/include/asm/kvm_booke.h
	arch/powerpc/include/asm/kvm_book3s.h

Which approach do you prefer?

> 
> > int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
> >                            unsigned int inst, int *advance)
> > {
> > @@ -89,6 +100,7 @@ int kvmppc_core_emulate_op(struct kvm_run *run,
> struct kvm_vcpu *vcpu,
> > 	int ra = get_ra(inst);
> > 	int rb = get_rb(inst);
> > 	int rt = get_rt(inst);
> > +	gva_t ea;
> >
> > 	switch (get_op(inst)) {
> > 	case 31:
> > @@ -113,15 +125,18 @@ int kvmppc_core_emulate_op(struct kvm_run *run,
> struct kvm_vcpu *vcpu,
> > 			break;
> >
> > 		case XOP_TLBSX:
> > -			emulated = kvmppc_e500_emul_tlbsx(vcpu,rb);
> > +			ea = kvmppc_get_ea_indexed(vcpu, ra, rb);
> > +			emulated = kvmppc_e500_emul_tlbsx(vcpu, ea);
> > 			break;
> >
> > 		case XOP_TLBILX:
> > -			emulated = kvmppc_e500_emul_tlbilx(vcpu, rt, ra, rb);
> > +			ea = kvmppc_get_ea_indexed(vcpu, ra, rb);
> > +			emulated = kvmppc_e500_emul_tlbilx(vcpu, rt, ea);
> 
> What's the point in hiding ra+rb, but not rt? I like the idea of hiding
> the register semantics, but please move rt into a local variable that
> gets passed as pointer to kvmppc_e500_emul_tlbilx.

Why to send it as a pointer? rt which should be rather named t in this case
is an [in] value for tlbilx, according to section 6.11.4.9 in the PowerISA 2.06b.

-Mike

RE: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in sregs

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: Alexander Graf [mailto:agraf@suse.de]
> Sent: Wednesday, July 04, 2012 4:34 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> Subject: Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR
> support in sregs
> 
> 
> On 25.06.2012, at 14:26, Mihai Caraman wrote:
> 
> > Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
> > for 64-bit hosts.
> 
> Please also implement a ONE_REG interface while at it. Over time, I'd
> like to move towards ONE_REG instead of the messy regs/sregs API.

ONE_REG doesn't seem to be implemented at all for book3e, I looked at
kvm_vcpu_ioctl_set_one_reg/kvm_vcpu_ioctl_get_one_reg in booke.c file.

I can take care of it soon but in a different patch set. It's ok like this?

-Mike

Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in sregs

[Alexander Graf]

On 07/05/2012 01:49 PM, Caraman Mihai Claudiu-B02008 wrote:
>> -----Original Message-----
>> From: Alexander Graf [mailto:agraf@suse.de]
>> Sent: Wednesday, July 04, 2012 4:34 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
>> Subject: Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR
>> support in sregs
>>
>>
>> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>>
>>> Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
>>> for 64-bit hosts.
>> Please also implement a ONE_REG interface while at it. Over time, I'd
>> like to move towards ONE_REG instead of the messy regs/sregs API.
> ONE_REG doesn't seem to be implemented at all for book3e, I looked at
> kvm_vcpu_ioctl_set_one_reg/kvm_vcpu_ioctl_get_one_reg in booke.c file.
>
> I can take care of it soon but in a different patch set. It's ok like this?

Do it in a different patch, but as part of this patch set.


Alex

RE: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in sregs

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: Alexander Graf [mailto:agraf@suse.de]
> Sent: Thursday, July 05, 2012 3:13 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> Subject: Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR
> support in sregs
> 
> On 07/05/2012 01:49 PM, Caraman Mihai Claudiu-B02008 wrote:
> >> -----Original Message-----
> >> From: Alexander Graf [mailto:agraf@suse.de]
> >> Sent: Wednesday, July 04, 2012 4:34 PM
> >> To: Caraman Mihai Claudiu-B02008
> >> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> >> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> >> Subject: Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR
> >> support in sregs
> >>
> >>
> >> On 25.06.2012, at 14:26, Mihai Caraman wrote:
> >>
> >>> Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
> >>> for 64-bit hosts.
> >> Please also implement a ONE_REG interface while at it. Over time, I'd
> >> like to move towards ONE_REG instead of the messy regs/sregs API.
> > ONE_REG doesn't seem to be implemented at all for book3e, I looked at
> > kvm_vcpu_ioctl_set_one_reg/kvm_vcpu_ioctl_get_one_reg in booke.c file.
> >
> > I can take care of it soon but in a different patch set. It's ok like
> this?
> 
> Do it in a different patch, but as part of this patch set.

Hmm ... then if you don't disagree I will do it as a prerequisite patch since I want
to keep this patchset strictly for 64-bit support.
I am not familiar with ONE_REG, is qemu tailored to use it? I need a way to test it.

-Mike

RE: [RFC PATCH 13/17] PowerPC: booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> Sent: Wednesday, June 27, 2012 1:16 AM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; qemu-ppc@nongnu.org; Anton Blanchard
> Subject: Re: [RFC PATCH 13/17] PowerPC: booke64: Use SPRG0/3 scratch for
> bolted TLB miss & crit int
> 
> On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
> > Embedded.Hypervisor category defines GSPRG0..3 physical registers for
> guests.
> > Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise
> guest
> > SPRG4-7 registers will be clobbered.
> > For bolted TLB miss exception handlers, which is the version currently
> > supported by KVM, use SPRN_SPRG_GEN_SCRATCH (aka SPRG0) instead of
> > SPRN_SPRG_TLB_SCRATCH (aka SPRG6) and replace TLB with GEN PACA slots
> to
> > keep consitency.
> > For critical exception handler use SPRG3 instead of SPRG7.
> 
> Beware with SPRG3 usage. It's user space visible and we plan to use it
> for other things (see Anton's patch to stick topology information in
> there for use by the vdso). If you clobber it, you may want to restore
> it later.

In booke3e case SPRG3 will not be clobbered by the guests which access GSPRG3,
but by the host exception handler. This means that we will have to restore SPRG3
even in the absence of KVM.

My proposal is to add a PACA slot for r13 and save it in the same way you did with
r12 in TLB_MISS_PROLOG. Then we can restore SPRG3 right in the prolog thus also
avoiding to deal with it in KVM.

The EXCEPTION_PROLOG is a common define for GEN/DBG/CRIT/MC, we use addition defines
to specialize just the CRIT case.

> I think Anton's patch should put the "proper" value we want in the PACA
> anyway since we also need to restore it on exit from KVM, so you can
> still use it as scratch, just restore the value before going to C.

I just saw last iteration of Anton's vsdo patch that matches your description.

Cheers,
-Mike

Re: [Qemu-ppc] [RFC PATCH 04/17] KVM: PPC64: booke: Add guest computation mode for irq delivery

[Scott Wood]

On 07/04/2012 08:40 AM, Alexander Graf wrote:
> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>> @@ -381,7 +386,8 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
>> 			set_guest_esr(vcpu, vcpu->arch.queued_esr);
>> 		if (update_dear == true)
>> 			set_guest_dear(vcpu, vcpu->arch.queued_dear);
>> -		kvmppc_set_msr(vcpu, vcpu->arch.shared->msr & msr_mask);
>> +		kvmppc_set_msr(vcpu, (vcpu->arch.shared->msr & msr_mask)
>> +				| msr_cm);
> 
> Please split this computation out into its own variable and apply the masking regardless. Something like
> 
> ulong new_msr = vcpu->arch.shared->msr;
> if (vcpu->arch.epcr & SPRN_EPCR_ICM)
>     new_msr |= MSR_CM;
> new_msr &= msr_mask;
> kvmppc_set_msr(vcpu, new_msr);

This will fail to clear MSR[CM] in the odd but legal situation where you
have MSR[CM] set but EPCR[ICM] unset.

-Scott

Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Scott Wood]

On 07/04/2012 01:15 PM, Caraman Mihai Claudiu-B02008 wrote:
>> ________________________________________
>> From: Alexander Graf [agraf@suse.de]
>> Sent: Wednesday, July 04, 2012 6:45 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: <kvm-ppc@vger.kernel.org>; KVM list; linuxppc-dev; qemu-ppc@nongnu.org List; Benjamin Herrenschmidt
>> Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks
>>
>> On 04.07.2012, at 17:27, Caraman Mihai Claudiu-B02008 wrote:
>>
>>>> -----Original Message-----
>>>> From: Alexander Graf [mailto:agraf@suse.de]
>>>> Sent: Wednesday, July 04, 2012 5:30 PM
>>>> To: Caraman Mihai Claudiu-B02008
>>>> Cc: <kvm-ppc@vger.kernel.org>; KVM list; linuxppc-dev; qemu-
>>>> ppc@nongnu.org List; Benjamin Herrenschmidt
>>>> Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM
>>>> kernel hooks
>>>>
>>>>
>>>> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>>>>
>>>>> Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit
>>>> booke
>>>>> see head_fsl_booke.S file. Extend interrupt handlers' parameter list
>>>> with
>>>>> interrupt vector numbers to accomodate the macro. Rework Guest Doorbell
>>>>> handler to use the proper GSRRx save/restore registers.
>>>>> Only the bolted version of tlb miss handers is addressed now.
>>>>>
>>>>> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
>>>>> ---
>>>>> arch/powerpc/kernel/exceptions-64e.S |  114 ++++++++++++++++++++++++---
>>>> -------
>>>>> arch/powerpc/mm/tlb_low_64e.S        |   14 +++-
>>>>> 2 files changed, 92 insertions(+), 36 deletions(-)
>>>>>
>>>>> diff --git a/arch/powerpc/kernel/exceptions-64e.S
>>>> b/arch/powerpc/kernel/exceptions-64e.S
>>>>> index 06f7aec..a60f81f 100644
>>>>> --- a/arch/powerpc/kernel/exceptions-64e.S
>>>>> +++ b/arch/powerpc/kernel/exceptions-64e.S
>>>>> @@ -25,6 +25,8 @@
>>>>> #include <asm/ppc-opcode.h>
>>>>> #include <asm/mmu.h>
>>>>> #include <asm/hw_irq.h>
>>>>> +#include <asm/kvm_asm.h>
>>>>> +#include <asm/kvm_booke_hv_asm.h>
>>>>>
>>>>> /* XXX This will ultimately add space for a special exception save
>>>>> *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
>>>>> @@ -34,13 +36,24 @@
>>>>> */
>>>>> #define     SPECIAL_EXC_FRAME_SIZE  INT_FRAME_SIZE
>>>>>
>>>>> +#ifdef CONFIG_KVM_BOOKE_HV
>>>>> +#define KVM_BOOKE_HV_MFSPR(reg, spr)                               \
>>>>> +   BEGIN_FTR_SECTION                                       \
>>>>> +           mfspr   reg, spr;                               \
>>>>> +   END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
>>>>> +#else
>>>>> +#define KVM_BOOKE_HV_MFSPR(reg, spr)
>>>>> +#endif
>>>>
>>>> Bleks - this is ugly.
>>>
>>> I agree :) But I opted to keep the optimizations done for 32-bit.
>>>
>>>> Do we really need to open-code the #ifdef here?
>>>
>>> 32-bit implementation fortunately use asm macros, we can't nest defines.
>>>
>>>> Can't the feature section code determine that the feature is disabled and
>>>> just always not include the code?
>>>
>>> CPU_FTR_EMB_HV is set even if KVM is not configured.
>>
>> I don't get the point then. Why not have the whole DO_KVM masked under FTR_SECTION_IFSET(CPU_FTR_EMB_HV)? Are there book3s_64 implementations without HV? 
> 
> I guess you refer to book3e_64. I don't know all implementations but Embedded.HV category is optional.
> 
>> Can't we just mfspr unconditionally in DO_KVM?
> 
> I think Scott should better answer this question, I don't know why he opted for the other approach.

That was on 32-bit, where some of DO_KVM's users want SRR1 for their own
purposes.

>>>>> -.macro tlb_prolog_bolted addr
>>>>> +.macro tlb_prolog_bolted intnum addr
>>>>>     mtspr   SPRN_SPRG_TLB_SCRATCH,r13
>>>>>     mfspr   r13,SPRN_SPRG_PACA
>>>>>     std     r10,PACA_EXTLB+EX_TLB_R10(r13)
>>>>>     mfcr    r10
>>>>>     std     r11,PACA_EXTLB+EX_TLB_R11(r13)
>>>>> +#ifdef CONFIG_KVM_BOOKE_HV
>>>>> +BEGIN_FTR_SECTION
>>>>> +   mfspr   r11, SPRN_SRR1
>>>>> +END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
>>>>> +#endif
>>>>
>>>> This thing really should vanish behind DO_KVM :)
>>>
>>> Then let's do it first for 32-bit ;)
>>
>> You could #ifdef it in DO_KVM for 64-bit for now. IIRC it's not done on 32-bit because the register value is used even beyond DO_KVM there.
> 
> Nope, 32-bit code is also guarded by CONFIG_KVM_BOOKE_HV.

Only in the TLB miss handlers, not the normal exception prolog.

-Scott

Re: [Qemu-ppc] [RFC PATCH 04/17] KVM: PPC64: booke: Add guest computation mode for irq delivery

[Alexander Graf]

On 06.07.2012, at 01:51, Scott Wood <scottwood@freescale.com> wrote:

> On 07/04/2012 08:40 AM, Alexander Graf wrote:
>> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>>> @@ -381,7 +386,8 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
>>>            set_guest_esr(vcpu, vcpu->arch.queued_esr);
>>>        if (update_dear == true)
>>>            set_guest_dear(vcpu, vcpu->arch.queued_dear);
>>> -        kvmppc_set_msr(vcpu, vcpu->arch.shared->msr & msr_mask);
>>> +        kvmppc_set_msr(vcpu, (vcpu->arch.shared->msr & msr_mask)
>>> +                | msr_cm);
>> 
>> Please split this computation out into its own variable and apply the masking regardless. Something like
>> 
>> ulong new_msr = vcpu->arch.shared->msr;
>> if (vcpu->arch.epcr & SPRN_EPCR_ICM)
>>    new_msr |= MSR_CM;
>> new_msr &= msr_mask;
>> kvmppc_set_msr(vcpu, new_msr);
> 
> This will fail to clear MSR[CM] in the odd but legal situation where you
> have MSR[CM] set but EPCR[ICM] unset.

Ah. Good point. Then leave the msr_mask logic as before and only stretch it out into its own variable.

Alex

> 
> -Scott
> 

Re: [RFC PATCH 08/17] KVM: PPC: e500mc: Fix tlbilx emulation for 64-bit guests

[Alexander Graf]

On 25.06.2012, at 14:26, Mihai Caraman wrote:

> tlbilxva emulation was using an u32 variable for guest effective address.
> Replace it with gva_t type to handle 64-bit guests.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>

Thanks, applied to kvm-ppc-next.


Alex

RE: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> Sent: Thursday, July 05, 2012 1:26 AM
> To: Alexander Graf
> Cc: Caraman Mihai Claudiu-B02008; <kvm-ppc@vger.kernel.org>; KVM list;
> linuxppc-dev; qemu-ppc@nongnu.org List
> Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM
> kernel hooks
> 
> On Wed, 2012-07-04 at 16:29 +0200, Alexander Graf wrote:
> 
> > > +#ifdef CONFIG_KVM_BOOKE_HV
> > > +#define KVM_BOOKE_HV_MFSPR(reg, spr)				\
> > > +	BEGIN_FTR_SECTION					\
> > > +		mfspr	reg, spr;			  	\
> > > +	END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
> > > +#else
> > > +#define KVM_BOOKE_HV_MFSPR(reg, spr)
> > > +#endif
> >
> > Bleks - this is ugly. Do we really need to open-code the #ifdef here?
> > Can't the feature section code determine that the feature is disabled
> > and just always not include the code?
> 
> You can't but in any case I don't see the point of the conditional here,
> we'll eventually have to load srr1 no ? We can move the load up to here
> in all cases or can't we ? 

I like the idea, but there is a problem with addition macros which may clobber
r11 and PROLOG_ADDITION_MASKABLE_GEN is such a case.

> If really not, we could have it inside DO_KVM and be done with it no ?

32-bit exception prolog loads srr1 unconditionally, as Alex and Scott mentioned
earlier, so we will be suboptimal for this case.

-Mike

RE: [Qemu-ppc] [RFC PATCH 09/17] KVM: PPC64: booke: Hard disable interrupts when entering guest

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+mihai.caraman=freescale.com@lists.ozlabs.org] On Behalf Of
> Benjamin Herrenschmidt
> Sent: Thursday, July 05, 2012 1:21 AM
> To: Alexander Graf
> Cc: qemu-ppc@nongnu.org List; Caraman Mihai Claudiu-B02008; linuxppc-dev;
> KVM list; <kvm-ppc@vger.kernel.org>
> Subject: Re: [Qemu-ppc] [RFC PATCH 09/17] KVM: PPC64: booke: Hard disable
> interrupts when entering guest
> 
> On Wed, 2012-07-04 at 16:14 +0200, Alexander Graf wrote:
> > > +#ifdef CONFIG_64BIT
> > > +#define _hard_irq_disable() hard_irq_disable()
> > > +#else
> > > +#define _hard_irq_disable() local_irq_disable()
> > > +#endif
> >
> > So you only swap out the disable bit, but not the enable one? Ben,
> > would this work out?
> 
> hard_irq_disable() both soft and hard disable. local_irq_enable() will
> see that irqs are hard disabled and will hard enable.
> 
> However, there's a nastier discrepancy above: local_irq_disable will
> properly inform lockdep that we are disabling, while hard_irq_disable
> won't.
> 
> Arguably we might want to fix that inside hard_irq_disable() itself...
> 
> Also you need to be careful. If you are coming with interrupts already
> enabled, it's fine, but if you have interrupts soft disabled, then
> you hard disable, before you enter the guest you probably want to
> check if anything was left "pending" and cancel the entering of the
> guest if that is the case.

On which cases I can find interrupts soft disabled if I call local_irq_enable()
ahead? Can this happen when my kernel task is scheduled? 

I presume that if I call hard_irq_disable() before entering the guest, a guest exit
will find interrupts soft disabled.

-Mike

Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Alexander Graf]

On 07.07.2012, at 00:33, Caraman Mihai Claudiu-B02008 wrote:

>> -----Original Message-----
>> From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
>> Sent: Thursday, July 05, 2012 1:26 AM
>> To: Alexander Graf
>> Cc: Caraman Mihai Claudiu-B02008; <kvm-ppc@vger.kernel.org>; KVM list;
>> linuxppc-dev; qemu-ppc@nongnu.org List
>> Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM
>> kernel hooks
>> 
>> On Wed, 2012-07-04 at 16:29 +0200, Alexander Graf wrote:
>> 
>>>> +#ifdef CONFIG_KVM_BOOKE_HV
>>>> +#define KVM_BOOKE_HV_MFSPR(reg, spr)				\
>>>> +	BEGIN_FTR_SECTION					\
>>>> +		mfspr	reg, spr;			  	\
>>>> +	END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
>>>> +#else
>>>> +#define KVM_BOOKE_HV_MFSPR(reg, spr)
>>>> +#endif
>>> 
>>> Bleks - this is ugly. Do we really need to open-code the #ifdef here?
>>> Can't the feature section code determine that the feature is disabled
>>> and just always not include the code?
>> 
>> You can't but in any case I don't see the point of the conditional here,
>> we'll eventually have to load srr1 no ? We can move the load up to here
>> in all cases or can't we ? 
> 
> I like the idea, but there is a problem with addition macros which may clobber
> r11 and PROLOG_ADDITION_MASKABLE_GEN is such a case.

Mike -v please :)


Alex

RE: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Caraman Mihai Claudiu-B02008]

>________________________________________
>From: Alexander Graf [agraf@suse.de]
>Sent: Saturday, July 07, 2012 2:11 AM
>To: Caraman Mihai Claudiu-B02008
>Cc: Benjamin Herrenschmidt; <kvm-ppc@vger.kernel.org>; KVM list; linuxppc-dev; qemu-ppc@nongnu.org List
>Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks
>
>On 07.07.2012, at 00:33, Caraman Mihai Claudiu-B02008 wrote:
>
>>> -----Original Message-----
>>> From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
>>> Sent: Thursday, July 05, 2012 1:26 AM
>>> To: Alexander Graf
>>> Cc: Caraman Mihai Claudiu-B02008; <kvm-ppc@vger.kernel.org>; KVM list;
>>> linuxppc-dev; qemu-ppc@nongnu.org List
>>> Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM
>>> kernel hooks
>>>
>>> You can't but in any case I don't see the point of the conditional here,
>>> we'll eventually have to load srr1 no ? We can move the load up to here
>>> in all cases or can't we ?
>>
>> I like the idea, but there is a problem with addition macros which may clobber
>> r11 and PROLOG_ADDITION_MASKABLE_GEN is such a case.
>
>Mike -v please :)

Ben suggested something like this:
	
 #define EXCEPTION_PROLOG(n, type, addition) \
 	mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
 	mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
 	std r10,PACA_EX##type+EX_R10(r13); \
 	std r11,PACA_EX##type+EX_R11(r13); \
 	mfcr r10; /* save CR */ \	
+	mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
	DO_KVM	intnum,srr1; \
 	addition; /* additional code for that exc. */ \
 	std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
 	stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
-	mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
 	type##_SET_KSTACK; /* get special stack if necessary */\
 	andi. r10,r11,MSR_PR; /* save stack pointer */ \

But one of the addition looks like this:
	
 #define PROLOG_ADDITION_MASKABLE_GEN(n) \
 	lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
	cmpwi cr0,r11,0; /* yes -> go out of line */ \
	beq masked_interrupt_book3e_##n	

So for maskable gen we end up with:

 #define EXCEPTION_PROLOG(n, type, addition) \
 	mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
 	mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
 	std r10,PACA_EX##type+EX_R10(r13); \
 	std r11,PACA_EX##type+EX_R11(r13); \
 	mfcr r10; /* save CR */ \
	mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
 	DO_KVM	intnum,srr1; \
	lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
	cmpwi cr0,r11,0; /* yes -> go out of line */ \
	beq masked_interrupt_book3e_##n	\
	std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
 	stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
 	type##_SET_KSTACK; /* get special stack if necessary */\
 	andi. r10,r11,MSR_PR; /* save stack pointer */ \
	
This affects the last asm line, we load srr1 into r11 but clobber it in-between.
We need a spare register for maskable gen addition. I think we can free r10 sooner
and used it in addition like this:

 #define EXCEPTION_PROLOG(n, type, addition) \
 	mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
 	mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \		
 	std r10,PACA_EX##type+EX_R10(r13); \
 	std r11,PACA_EX##type+EX_R11(r13); \
+	mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
	mfcr r10; /* save CR */ \
+ 	stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
 	DO_KVM	intnum,srr1; \
-	lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
-	cmpwi cr0,r11,0; /* yes -> go out of line */ \
+	lbz r10,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
+	cmpwi cr0,r10,0; /* yes -> go out of line */ \
	beq masked_interrupt_book3e_##n	\
 	std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
- 	stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
-	mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
 	type##_SET_KSTACK; /* get special stack if necessary */\
 	andi. r10,r11,MSR_PR; /* save stack pointer */ \
	
-Mike

Re: [RFC PATCH 06/17] KVM: PPC: e500: Add emulation helper for getting instruction ea

[Alexander Graf]

On 05.07.2012, at 13:39, Caraman Mihai Claudiu-B02008 wrote:

>> -----Original Message-----
>> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
>> owner@vger.kernel.org] On Behalf Of Alexander Graf
>> Sent: Wednesday, July 04, 2012 4:56 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
>> Subject: Re: [RFC PATCH 06/17] KVM: PPC: e500: Add emulation helper for
>> getting instruction ea
>> 
>> 
>> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>> 
>>> Add emulation helper for getting instruction ea and refactor tlb
>> instruction
>>> emulation to use it.
>>> 
>>> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
>>> ---
>>> arch/powerpc/kvm/e500.h         |    6 +++---
>>> arch/powerpc/kvm/e500_emulate.c |   21 ++++++++++++++++++---
>>> arch/powerpc/kvm/e500_tlb.c     |   23 ++++++-----------------
>>> 3 files changed, 27 insertions(+), 23 deletions(-)
>>> 
>>> diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
>>> index 3e31098..70bfed4 100644
>>> --- a/arch/powerpc/kvm/e500.h
>>> +++ b/arch/powerpc/kvm/e500.h
>>> @@ -130,9 +130,9 @@ int kvmppc_e500_emul_mt_mmucsr0(struct
>> kvmppc_vcpu_e500 *vcpu_e500,
>>> 				ulong value);
>>> int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu);
>>> int kvmppc_e500_emul_tlbre(struct kvm_vcpu *vcpu);
>>> -int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, int ra, int rb);
>>> -int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, int ra, int
>> rb);
>>> -int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, int rb);
>>> +int kvmppc_e500_emul_tlbivax(struct kvm_vcpu *vcpu, gva_t ea);
>>> +int kvmppc_e500_emul_tlbilx(struct kvm_vcpu *vcpu, int rt, gva_t ea);
>>> +int kvmppc_e500_emul_tlbsx(struct kvm_vcpu *vcpu, gva_t ea);
>>> int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 *vcpu_e500);
>>> void kvmppc_e500_tlb_uninit(struct kvmppc_vcpu_e500 *vcpu_e500);
>>> 
>>> diff --git a/arch/powerpc/kvm/e500_emulate.c
>> b/arch/powerpc/kvm/e500_emulate.c
>>> index 8b99e07..81288f7 100644
>>> --- a/arch/powerpc/kvm/e500_emulate.c
>>> +++ b/arch/powerpc/kvm/e500_emulate.c
>>> @@ -82,6 +82,17 @@ static int kvmppc_e500_emul_msgsnd(struct kvm_vcpu
>> *vcpu, int rb)
>>> }
>>> #endif
>>> 
>>> +static inline ulong kvmppc_get_ea_indexed(struct kvm_vcpu *vcpu, int
>> ra, int rb)
>>> +{
>>> +	ulong ea;
>>> +
>>> +	ea = kvmppc_get_gpr(vcpu, rb);
>>> +	if (ra)
>>> +		ea += kvmppc_get_gpr(vcpu, ra);
>>> +
>>> +	return ea;
>>> +}
>>> +
>> 
>> Please move this one to arch/powerpc/include/asm/kvm_ppc.h.
> 
> Yep. This is similar with what I had in my internal version before emulation
> refactoring took place upstream. The only difference is that I split the embedded
> and server implementation touching this files:
> 	arch/powerpc/include/asm/kvm_booke.h
> 	arch/powerpc/include/asm/kvm_book3s.h
> 
> Which approach do you prefer?

This is generic code to me, so it shouldn't go into booke/book3s specific files.

> 
>> 
>>> int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
>>>                           unsigned int inst, int *advance)
>>> {
>>> @@ -89,6 +100,7 @@ int kvmppc_core_emulate_op(struct kvm_run *run,
>> struct kvm_vcpu *vcpu,
>>> 	int ra = get_ra(inst);
>>> 	int rb = get_rb(inst);
>>> 	int rt = get_rt(inst);
>>> +	gva_t ea;
>>> 
>>> 	switch (get_op(inst)) {
>>> 	case 31:
>>> @@ -113,15 +125,18 @@ int kvmppc_core_emulate_op(struct kvm_run *run,
>> struct kvm_vcpu *vcpu,
>>> 			break;
>>> 
>>> 		case XOP_TLBSX:
>>> -			emulated = kvmppc_e500_emul_tlbsx(vcpu,rb);
>>> +			ea = kvmppc_get_ea_indexed(vcpu, ra, rb);
>>> +			emulated = kvmppc_e500_emul_tlbsx(vcpu, ea);
>>> 			break;
>>> 
>>> 		case XOP_TLBILX:
>>> -			emulated = kvmppc_e500_emul_tlbilx(vcpu, rt, ra, rb);
>>> +			ea = kvmppc_get_ea_indexed(vcpu, ra, rb);
>>> +			emulated = kvmppc_e500_emul_tlbilx(vcpu, rt, ea);
>> 
>> What's the point in hiding ra+rb, but not rt? I like the idea of hiding
>> the register semantics, but please move rt into a local variable that
>> gets passed as pointer to kvmppc_e500_emul_tlbilx.
> 
> Why to send it as a pointer? rt which should be rather named t in this case
> is an [in] value for tlbilx, according to section 6.11.4.9 in the PowerISA 2.06b.

Because usually rt in the PPC ISA denotes a _t_arget _r_egister. The field here really is called "T" to denote the _t_ype of the operation which you correctly pointed out. Could you please change this misnaming along the way and mask it accordingly?


Alex

Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR support in sregs

[Alexander Graf]

On 05.07.2012, at 14:54, Caraman Mihai Claudiu-B02008 wrote:

>> -----Original Message-----
>> From: Alexander Graf [mailto:agraf@suse.de]
>> Sent: Thursday, July 05, 2012 3:13 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
>> Subject: Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR
>> support in sregs
>> 
>> On 07/05/2012 01:49 PM, Caraman Mihai Claudiu-B02008 wrote:
>>>> -----Original Message-----
>>>> From: Alexander Graf [mailto:agraf@suse.de]
>>>> Sent: Wednesday, July 04, 2012 4:34 PM
>>>> To: Caraman Mihai Claudiu-B02008
>>>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>>>> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
>>>> Subject: Re: [Qemu-ppc] [RFC PATCH 03/17] KVM: PPC64: booke: Add EPCR
>>>> support in sregs
>>>> 
>>>> 
>>>> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>>>> 
>>>>> Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
>>>>> for 64-bit hosts.
>>>> Please also implement a ONE_REG interface while at it. Over time, I'd
>>>> like to move towards ONE_REG instead of the messy regs/sregs API.
>>> ONE_REG doesn't seem to be implemented at all for book3e, I looked at
>>> kvm_vcpu_ioctl_set_one_reg/kvm_vcpu_ioctl_get_one_reg in booke.c file.
>>> 
>>> I can take care of it soon but in a different patch set. It's ok like
>> this?
>> 
>> Do it in a different patch, but as part of this patch set.
> 
> Hmm ... then if you don't disagree I will do it as a prerequisite patch since I want
> to keep this patchset strictly for 64-bit support.

I don't understand? You just make the same functionality available through 2 interfaces to user space.

> I am not familiar with ONE_REG, is qemu tailored to use it? I need a way to test it.

ONE_REG is just a more extensible ioctl. Just read up on it in the documentation and you'll see what I mean :)


Alex

Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Alexander Graf]

On 07.07.2012, at 10:39, Caraman Mihai Claudiu-B02008 wrote:

>> ________________________________________
>> From: Alexander Graf [agraf@suse.de]
>> Sent: Saturday, July 07, 2012 2:11 AM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: Benjamin Herrenschmidt; <kvm-ppc@vger.kernel.org>; KVM list; linuxppc-dev; qemu-ppc@nongnu.org List
>> Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks
>> 
>> On 07.07.2012, at 00:33, Caraman Mihai Claudiu-B02008 wrote:
>> 
>>>> -----Original Message-----
>>>> From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
>>>> Sent: Thursday, July 05, 2012 1:26 AM
>>>> To: Alexander Graf
>>>> Cc: Caraman Mihai Claudiu-B02008; <kvm-ppc@vger.kernel.org>; KVM list;
>>>> linuxppc-dev; qemu-ppc@nongnu.org List
>>>> Subject: Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM
>>>> kernel hooks
>>>> 
>>>> You can't but in any case I don't see the point of the conditional here,
>>>> we'll eventually have to load srr1 no ? We can move the load up to here
>>>> in all cases or can't we ?
>>> 
>>> I like the idea, but there is a problem with addition macros which may clobber
>>> r11 and PROLOG_ADDITION_MASKABLE_GEN is such a case.
>> 
>> Mike -v please :)
> 
> Ben suggested something like this:
> 	
> #define EXCEPTION_PROLOG(n, type, addition) \
> 	mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
> 	mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
> 	std r10,PACA_EX##type+EX_R10(r13); \
> 	std r11,PACA_EX##type+EX_R11(r13); \
> 	mfcr r10; /* save CR */ \	
> +	mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
> 	DO_KVM	intnum,srr1; \
> 	addition; /* additional code for that exc. */ \
> 	std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
> 	stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
> -	mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
> 	type##_SET_KSTACK; /* get special stack if necessary */\
> 	andi. r10,r11,MSR_PR; /* save stack pointer */ \
> 
> But one of the addition looks like this:
> 	
> #define PROLOG_ADDITION_MASKABLE_GEN(n) \
> 	lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
> 	cmpwi cr0,r11,0; /* yes -> go out of line */ \
> 	beq masked_interrupt_book3e_##n	
> 
> So for maskable gen we end up with:
> 
> #define EXCEPTION_PROLOG(n, type, addition) \
> 	mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
> 	mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
> 	std r10,PACA_EX##type+EX_R10(r13); \
> 	std r11,PACA_EX##type+EX_R11(r13); \
> 	mfcr r10; /* save CR */ \
> 	mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
> 	DO_KVM	intnum,srr1; \
> 	lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
> 	cmpwi cr0,r11,0; /* yes -> go out of line */ \
> 	beq masked_interrupt_book3e_##n	\
> 	std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
> 	stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
> 	type##_SET_KSTACK; /* get special stack if necessary */\
> 	andi. r10,r11,MSR_PR; /* save stack pointer */ \
> 	
> This affects the last asm line, we load srr1 into r11 but clobber it in-between.
> We need a spare register for maskable gen addition. I think we can free r10 sooner
> and used it in addition like this:

Ah, makes sense, yes.

> 
> #define EXCEPTION_PROLOG(n, type, addition) \
> 	mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
> 	mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \		
> 	std r10,PACA_EX##type+EX_R10(r13); \
> 	std r11,PACA_EX##type+EX_R11(r13); \

Or just free up another register early on, like here.


Alex

> +	mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
> 	mfcr r10; /* save CR */ \
> + 	stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
> 	DO_KVM	intnum,srr1; \
> -	lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
> -	cmpwi cr0,r11,0; /* yes -> go out of line */ \
> +	lbz r10,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
> +	cmpwi cr0,r10,0; /* yes -> go out of line */ \
> 	beq masked_interrupt_book3e_##n	\
> 	std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
> - 	stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
> -	mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
> 	type##_SET_KSTACK; /* get special stack if necessary */\
> 	andi. r10,r11,MSR_PR; /* save stack pointer */ \
> 	
> -Mike
> --
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Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Benjamin Herrenschmidt]

On Thu, 2012-07-12 at 00:25 +0200, Alexander Graf wrote:
> Or just free up another register early on, like here.

If you're going to do that, you want to measure the impact on null
syscall performance though.

Cheers,
Ben.

Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Alexander Graf]

On 12.07.2012, at 00:28, Benjamin Herrenschmidt wrote:

> On Thu, 2012-07-12 at 00:25 +0200, Alexander Graf wrote:
>> Or just free up another register early on, like here.
> 
> If you're going to do that, you want to measure the impact on null
> syscall performance though.

That should hold true for any change in that code, no?


Alex

Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Benjamin Herrenschmidt]

On Thu, 2012-07-12 at 00:35 +0200, Alexander Graf wrote:
> > On Thu, 2012-07-12 at 00:25 +0200, Alexander Graf wrote:
> >> Or just free up another register early on, like here.
> > 
> > If you're going to do that, you want to measure the impact on null
> > syscall performance though.
> 
> That should hold true for any change in that code, no?

Yes, but adding a gpr save is more invasive (you have to also load it
back later on & put it on the stack).

Cheers,
Ben.

Re: [Qemu-ppc] [RFC PATCH 12/17] PowerPC: booke64: Add DO_KVM kernel hooks

[Alexander Graf]

On 12.07.2012, at 00:43, Benjamin Herrenschmidt wrote:

> On Thu, 2012-07-12 at 00:35 +0200, Alexander Graf wrote:
>>> On Thu, 2012-07-12 at 00:25 +0200, Alexander Graf wrote:
>>>> Or just free up another register early on, like here.
>>> 
>>> If you're going to do that, you want to measure the impact on null
>>> syscall performance though.
>> 
>> That should hold true for any change in that code, no?
> 
> Yes, but adding a gpr save is more invasive (you have to also load it
> back later on & put it on the stack).

What's the usual cache line size like on these boxes? If you align it properly with r10 and r11 on the paca so that all 3 registers are in the same cache line, the load should be almost for free, no?


Alex

Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2 EPN mask for 64-bit

[Alexander Graf]

On 05.07.2012, at 13:14, Caraman Mihai Claudiu-B02008 wrote:

> 
> 
>> -----Original Message-----
>> From: Alexander Graf [mailto:agraf@suse.de]
>> Sent: Wednesday, July 04, 2012 4:50 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
>> Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2
>> EPN mask for 64-bit
>> 
>> 
>> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>> 
>>> Extend MAS2 EPN mask for 64-bit hosts, to retain most significant bits.
>>> Change get tlb eaddr to use this mask.
>> 
>> Please see section 6.11.4.8 in the PowerISA 2.06b:
>> 
>> MMU behavior is largely unaffected by whether the thread is in 32-bit
>> computation mode (MSRCM=0) or 64- bit computation mode (MSRCM=1). The
>> only differ- ences occur in the EPN field of the TLB entry and the EPN
>> field of MAS2. The differences are summarized here.
>> 
>> 	*  Executing a tlbwe instruction in 32-bit mode will set bits 0:31
>> of the TLB EPN field to zero unless MAS0ATSEL is set, in which case those
>> bits are not written to zero.
>> 	*  In 32-bit implementations, MAS2U can be used to read or write
>> EPN0:31 of MAS2.
>> 
>> So if MSR.CM is not set tlbwe should mask the upper 32 bits out - which
>> can happen regardless of CONFIG_64BIT.
> 
> MAS2_EPN reflects EPN field of MAS2 aka bits 0:51 (for MAV = 1.0) according
> to section 6.10.3.10 in the PowerISA 2.06b.
> 
> MAS2_EPN is not used in tlbwe execution emulation, we have MAS2_VAL define
> for this case.

So tlbe->mas2 is guaranteed to have the upper bits be 0 when MSR.CM=0?

> 
>> Also, we need to implement MAS2U, to potentially make the upper 32bits of
>> MAS2 available, right? But that one isn't as important as the first bit.
> 
> MAS2U is guest privileged why does it need special care?

Maybe it's mapped to the upper bits of GMAS2 automatically?

> Freescale core Manuals and EREF does not mention MAS2U so I think I our case
> it is not implemented.

Please check with a simple mfspr() test on real hw to see if it really isn't implemented.


Alex

RE: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2 EPN mask for 64-bit

[Caraman Mihai Claudiu-B02008]

> -----Original Message-----
> From: Alexander Graf [mailto:agraf@suse.de]
> Sent: Monday, October 08, 2012 1:11 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2
> EPN mask for 64-bit
> 
> 
> On 05.07.2012, at 13:14, Caraman Mihai Claudiu-B02008 wrote:
> 
> >
> >
> >> -----Original Message-----
> >> From: Alexander Graf [mailto:agraf@suse.de]
> >> Sent: Wednesday, July 04, 2012 4:50 PM
> >> To: Caraman Mihai Claudiu-B02008
> >> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> >> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
> >> Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2
> >> EPN mask for 64-bit
> >>
> >>
> >> On 25.06.2012, at 14:26, Mihai Caraman wrote:
> >>
> >>> Extend MAS2 EPN mask for 64-bit hosts, to retain most significant
> bits.
> >>> Change get tlb eaddr to use this mask.
> >>
> >> Please see section 6.11.4.8 in the PowerISA 2.06b:
> >>
> >> MMU behavior is largely unaffected by whether the thread is in 32-bit
> >> computation mode (MSRCM=0) or 64- bit computation mode (MSRCM=1). The
> >> only differ- ences occur in the EPN field of the TLB entry and the EPN
> >> field of MAS2. The differences are summarized here.
> >>
> >> 	*  Executing a tlbwe instruction in 32-bit mode will set bits 0:31
> >> of the TLB EPN field to zero unless MAS0ATSEL is set, in which case
> those
> >> bits are not written to zero.
> >> 	*  In 32-bit implementations, MAS2U can be used to read or write
> >> EPN0:31 of MAS2.
> >>
> >> So if MSR.CM is not set tlbwe should mask the upper 32 bits out -
> which
> >> can happen regardless of CONFIG_64BIT.
> >
> > MAS2_EPN reflects EPN field of MAS2 aka bits 0:51 (for MAV = 1.0)
> according
> > to section 6.10.3.10 in the PowerISA 2.06b.
> >
> > MAS2_EPN is not used in tlbwe execution emulation, we have MAS2_VAL
> define
> > for this case.
> 
> So tlbe->mas2 is guaranteed to have the upper bits be 0 when MSR.CM=0?

We chose to mask out mas2 upper bits on tlbwe emulation so gtlbe->mas2 will
respect this but vcpu->arch.shared->mas2 will not. tlb entry selection does not
require this treatment since EPN upper bits are not taken into consideration anyway.

> 
> >
> >> Also, we need to implement MAS2U, to potentially make the upper 32bits
> of
> >> MAS2 available, right? But that one isn't as important as the first
> bit.
> >
> > MAS2U is guest privileged why does it need special care?
> 
> Maybe it's mapped to the upper bits of GMAS2 automatically?

GMAS2?

> 
> > Freescale core Manuals and EREF does not mention MAS2U so I think I our
> case
> > it is not implemented.
> 
> Please check with a simple mfspr() test on real hw to see if it really
> isn't implemented.

I will try this with SPR number 0x277.

-Mike

Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2 EPN mask for 64-bit

[Alexander Graf]

On 08.10.2012, at 15:06, Caraman Mihai Claudiu-B02008 wrote:

>> -----Original Message-----
>> From: Alexander Graf [mailto:agraf@suse.de]
>> Sent: Monday, October 08, 2012 1:11 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
>> Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2
>> EPN mask for 64-bit
>> 
>> 
>> On 05.07.2012, at 13:14, Caraman Mihai Claudiu-B02008 wrote:
>> 
>>> 
>>> 
>>>> -----Original Message-----
>>>> From: Alexander Graf [mailto:agraf@suse.de]
>>>> Sent: Wednesday, July 04, 2012 4:50 PM
>>>> To: Caraman Mihai Claudiu-B02008
>>>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>>>> dev@lists.ozlabs.org; qemu-ppc@nongnu.org
>>>> Subject: Re: [Qemu-ppc] [RFC PATCH 05/17] KVM: PPC: booke: Extend MAS2
>>>> EPN mask for 64-bit
>>>> 
>>>> 
>>>> On 25.06.2012, at 14:26, Mihai Caraman wrote:
>>>> 
>>>>> Extend MAS2 EPN mask for 64-bit hosts, to retain most significant
>> bits.
>>>>> Change get tlb eaddr to use this mask.
>>>> 
>>>> Please see section 6.11.4.8 in the PowerISA 2.06b:
>>>> 
>>>> MMU behavior is largely unaffected by whether the thread is in 32-bit
>>>> computation mode (MSRCM=0) or 64- bit computation mode (MSRCM=1). The
>>>> only differ- ences occur in the EPN field of the TLB entry and the EPN
>>>> field of MAS2. The differences are summarized here.
>>>> 
>>>> 	*  Executing a tlbwe instruction in 32-bit mode will set bits 0:31
>>>> of the TLB EPN field to zero unless MAS0ATSEL is set, in which case
>> those
>>>> bits are not written to zero.
>>>> 	*  In 32-bit implementations, MAS2U can be used to read or write
>>>> EPN0:31 of MAS2.
>>>> 
>>>> So if MSR.CM is not set tlbwe should mask the upper 32 bits out -
>> which
>>>> can happen regardless of CONFIG_64BIT.
>>> 
>>> MAS2_EPN reflects EPN field of MAS2 aka bits 0:51 (for MAV = 1.0)
>> according
>>> to section 6.10.3.10 in the PowerISA 2.06b.
>>> 
>>> MAS2_EPN is not used in tlbwe execution emulation, we have MAS2_VAL
>> define
>>> for this case.
>> 
>> So tlbe->mas2 is guaranteed to have the upper bits be 0 when MSR.CM=0?
> 
> We chose to mask out mas2 upper bits on tlbwe emulation so gtlbe->mas2 will
> respect this but vcpu->arch.shared->mas2 will not. tlb entry selection does not
> require this treatment since EPN upper bits are not taken into consideration anyway.

That's fine. We don't control the contents of shared->mas2 anyway.

> 
>> 
>>> 
>>>> Also, we need to implement MAS2U, to potentially make the upper 32bits
>> of
>>>> MAS2 available, right? But that one isn't as important as the first
>> bit.
>>> 
>>> MAS2U is guest privileged why does it need special care?
>> 
>> Maybe it's mapped to the upper bits of GMAS2 automatically?
> 
> GMAS2?

Ah. The guest has direct control over the real MAS2. Oh well.

> 
>> 
>>> Freescale core Manuals and EREF does not mention MAS2U so I think I our
>> case
>>> it is not implemented.
>> 
>> Please check with a simple mfspr() test on real hw to see if it really
>> isn't implemented.
> 
> I will try this with SPR number 0x277.

Thanks :)


Alex