From mboxrd@z Thu Jan  1 00:00:00 1970
From: Scott Wood <scottwood@freescale.com>
Subject: Re: [RFC PATCH 13/17] PowerPC: booke64: Use SPRG0/3 scratch for bolted
 TLB miss & crit int
Date: Tue, 26 Jun 2012 17:24:08 -0500
Message-ID: <4FEA3688.5030603@freescale.com>
References: <1340627195-11544-1-git-send-email-mihai.caraman@freescale.com> <1340627195-11544-14-git-send-email-mihai.caraman@freescale.com>
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To: Mihai Caraman <mihai.caraman@freescale.com>
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On 06/25/2012 07:26 AM, Mihai Caraman wrote:
> Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
> Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
> SPRG4-7 registers will be clobbered.
> For bolted TLB miss exception handlers, which is the version currently
> supported by KVM, use SPRN_SPRG_GEN_SCRATCH (aka SPRG0) instead of
> SPRN_SPRG_TLB_SCRATCH (aka SPRG6) and replace TLB with GEN PACA slots to
> keep consitency.
> For critical exception handler use SPRG3 instead of SPRG7.

extlb is in the same cache line as other TLB stuff we need, while exgen
isn't.  Let's stick with extlb.

-Scott