From: "Shah, Amit" <Amit.Shah@amd.com>
To: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"dave.hansen@intel.com" <dave.hansen@intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
"x86@kernel.org" <x86@kernel.org>
Cc: "corbet@lwn.net" <corbet@lwn.net>,
"boris.ostrovsky@oracle.com" <boris.ostrovsky@oracle.com>,
"kai.huang@intel.com" <kai.huang@intel.com>,
"pawan.kumar.gupta@linux.intel.com"
<pawan.kumar.gupta@linux.intel.com>,
"jpoimboe@kernel.org" <jpoimboe@kernel.org>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"daniel.sneddon@linux.intel.com" <daniel.sneddon@linux.intel.com>,
"Lendacky, Thomas" <Thomas.Lendacky@amd.com>,
"seanjc@google.com" <seanjc@google.com>,
"mingo@redhat.com" <mingo@redhat.com>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"Moger, Babu" <Babu.Moger@amd.com>,
"Das1, Sandipan" <Sandipan.Das@amd.com>,
"hpa@zytor.com" <hpa@zytor.com>,
"peterz@infradead.org" <peterz@infradead.org>,
"bp@alien8.de" <bp@alien8.de>,
"Kaplan, David" <David.Kaplan@amd.com>
Subject: Re: [PATCH 1/2] x86: cpu/bugs: add support for AMD ERAPS feature
Date: Mon, 4 Nov 2024 08:58:41 +0000 [thread overview]
Message-ID: <4b23d73d450d284bbefc4f23d8a7f0798517e24e.camel@amd.com> (raw)
In-Reply-To: <05c12dec-3f39-4811-8e15-82cfd229b66a@intel.com>
On Thu, 2024-10-31 at 16:11 -0700, Dave Hansen wrote:
> On 10/31/24 08:39, Amit Shah wrote:
> ...
> > With the Enhanced Return Address Prediction Security feature, any
> > hardware TLB flush results in flushing of the RSB (aka RAP in AMD
> > spec).
> > This guarantees an RSB flush across context switches.
>
> Check out the APM, volume 2: "5.5.1 Process Context Identifier"
>
> ... when system software switches address spaces (by writing
> ...
> CR3[62:12]), the processor may use TLB mappings previously
> stored for that address space and PCID, providing that bit
> 63 of
> the source operand is set to 1.
>
> tl;dr: PCIDs mean you don't necessarily flush the TLB on context
> switches.
Right - thanks, I'll have to reword that to say the RSB is flushed
along with the TLB - so any action that causes the TLB to be flushed
will also cause the RSB to be flushed.
next prev parent reply other threads:[~2024-11-04 8:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-31 15:39 [PATCH 0/2] Add support for the ERAPS feature Amit Shah
2024-10-31 15:39 ` [PATCH 1/2] x86: cpu/bugs: add support for AMD " Amit Shah
2024-10-31 23:03 ` Pawan Gupta
2024-11-04 8:57 ` Shah, Amit
2024-11-04 14:52 ` Andrew Cooper
2024-11-04 15:00 ` Shah, Amit
2024-10-31 23:11 ` Dave Hansen
2024-11-04 8:58 ` Shah, Amit [this message]
2024-11-04 16:11 ` Dave Hansen
2024-11-04 16:13 ` Shah, Amit
2024-11-04 16:26 ` Dave Hansen
2024-11-04 17:22 ` Shah, Amit
2024-11-04 17:45 ` Dave Hansen
2024-11-05 0:04 ` Andrew Cooper
2024-11-05 10:39 ` Shah, Amit
2024-11-05 14:54 ` Kaplan, David
2024-11-05 16:19 ` Dave Hansen
2024-11-05 16:25 ` Shah, Amit
2024-10-31 15:39 ` [PATCH 2/2] x86: kvm: svm: add support for ERAPS and FLUSH_RAP_ON_VMRUN Amit Shah
2024-10-31 23:13 ` Pawan Gupta
2024-11-01 4:14 ` kernel test robot
2024-11-01 9:26 ` Amit Shah
2024-11-04 5:18 ` Borislav Petkov
2024-11-04 11:16 ` Shah, Amit
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