From: Like Xu <like.xu.linux@gmail.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>, kvm@vger.kernel.org
Subject: Re: [kvm-unit-tests PATCH v3 10/13] x86/pmu: Update testcases to cover Intel Arch PMU Version 1
Date: Tue, 18 Oct 2022 17:32:59 +0800 [thread overview]
Message-ID: <4b9d7939-ebd5-385d-d0cc-e95955e0238f@gmail.com> (raw)
In-Reply-To: <Yz4GtqyPIMCMsUEl@google.com>
All applied except pmu_clear_global_status_safe(). Thanks.
On 6/10/2022 6:35 am, Sean Christopherson wrote:
> On Fri, Aug 19, 2022, Like Xu wrote:
>> From: Like Xu <likexu@tencent.com>
>>
>> For most unit tests, the basic framework and use cases which test
>> any PMU counter do not require any changes, except for two things:
>>
>> - No access to registers introduced only in PMU version 2 and above;
>> - Expanded tolerance for testing counter overflows
>> due to the loss of uniform control of the gloabl_ctrl register
>>
>> Adding some pmu_version() return value checks can seamlessly support
>> Intel Arch PMU Version 1, while opening the door for AMD PMUs tests.
>
> Phrase this as a command so that it's crystal clear that this is what the patch
> does, as opposed to what the patch _can_ do.
>
>> Signed-off-by: Like Xu <likexu@tencent.com>
>> ---
>> x86/pmu.c | 64 +++++++++++++++++++++++++++++++++++++------------------
>> 1 file changed, 43 insertions(+), 21 deletions(-)
>>
>> diff --git a/x86/pmu.c b/x86/pmu.c
>> index 25fafbe..826472c 100644
>> --- a/x86/pmu.c
>> +++ b/x86/pmu.c
>> @@ -125,14 +125,19 @@ static struct pmu_event* get_counter_event(pmu_counter_t *cnt)
>>
>> static void global_enable(pmu_counter_t *cnt)
>> {
>> - cnt->idx = event_to_global_idx(cnt);
>> + if (pmu_version() < 2)
>
> Helper please.
>
>> + return;
>>
>> + cnt->idx = event_to_global_idx(cnt);
>> wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_CTRL) |
>> (1ull << cnt->idx));
>> }
>>
>> static void global_disable(pmu_counter_t *cnt)
>> {
>> + if (pmu_version() < 2)
>> + return;
>> +
>> wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_CTRL) &
>> ~(1ull << cnt->idx));
>> }
>> @@ -301,7 +306,10 @@ static void check_counter_overflow(void)
>> count = cnt.count;
>>
>> /* clear status before test */
>> - wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_STATUS));
>> + if (pmu_version() > 1) {
>
> Should be a helper to use from an earlier patch.
>
> Hmm, looking forward, maybe have an upper level helper? E.g.
>
> void pmu_clear_global_status_safe(void)
> {
> if (!exists)
> return
>
> wrmsr(...);
> }
>
> Ignore this suggestion if these checks go away in the future.
>
>> + wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL,
>> + rdmsr(MSR_CORE_PERF_GLOBAL_STATUS));
>> + }
>>
>> report_prefix_push("overflow");
>>
>> @@ -327,13 +335,21 @@ static void check_counter_overflow(void)
>> cnt.config &= ~EVNTSEL_INT;
>> idx = event_to_global_idx(&cnt);
>> __measure(&cnt, cnt.count);
>> - report(cnt.count == 1, "cntr-%d", i);
>> +
>> + report(check_irq() == (i % 2), "irq-%d", i);
>> + if (pmu_version() > 1)
>
> Helper.
>
>> + report(cnt.count == 1, "cntr-%d", i);
>> + else
>> + report(cnt.count < 4, "cntr-%d", i);
>> +
>> + if (pmu_version() < 2)
>
> Helper.
>
>> + continue;
>> +
>> status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS);
>> report(status & (1ull << idx), "status-%d", i);
>> wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, status);
>> status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS);
>> report(!(status & (1ull << idx)), "status clear-%d", i);
>> - report(check_irq() == (i % 2), "irq-%d", i);
>> }
>>
>> report_prefix_pop();
>> @@ -440,8 +456,10 @@ static void check_running_counter_wrmsr(void)
>> report(evt.count < gp_events[1].min, "cntr");
>>
>> /* clear status before overflow test */
>> - wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL,
>> - rdmsr(MSR_CORE_PERF_GLOBAL_STATUS));
>> + if (pmu_version() > 1) {
>
> Helper. Curly braces aren't necessary.
>
>> + wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL,
>> + rdmsr(MSR_CORE_PERF_GLOBAL_STATUS));
>> + }
>>
>> start_event(&evt);
>>
>> @@ -453,8 +471,11 @@ static void check_running_counter_wrmsr(void)
>>
>> loop();
>> stop_event(&evt);
>> - status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS);
>> - report(status & 1, "status");
>> +
>> + if (pmu_version() > 1) {
>
> Helper.
>
>> + status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS);
>> + report(status & 1, "status");
>
> Can you opportunistically provide a better message than "status"?
>
>> + }
>>
>> report_prefix_pop();
>> }
>> @@ -474,8 +495,10 @@ static void check_emulated_instr(void)
>> };
>> report_prefix_push("emulated instruction");
>>
>> - wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL,
>> - rdmsr(MSR_CORE_PERF_GLOBAL_STATUS));
>> + if (pmu_version() > 1) {
>
> Helper, no curly braces. Ah, IIRC, kernel perf prefers curly braces if the code
> spans multiple lines. KVM and KUT does not.
OK.
>
>> + wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL,
>> + rdmsr(MSR_CORE_PERF_GLOBAL_STATUS));
>> + }
>>
>> start_event(&brnch_cnt);
>> start_event(&instr_cnt);
>> @@ -509,7 +532,8 @@ static void check_emulated_instr(void)
>> :
>> : "eax", "ebx", "ecx", "edx");
>>
>> - wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
>> + if (pmu_version() > 1)
>
> Helper.
>
>> + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
>>
>> stop_event(&brnch_cnt);
>> stop_event(&instr_cnt);
>> @@ -520,10 +544,13 @@ static void check_emulated_instr(void)
>> "instruction count");
>> report(brnch_cnt.count - brnch_start >= EXPECTED_BRNCH,
>> "branch count");
>> - // Additionally check that those counters overflowed properly.
>> - status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS);
>> - report(status & 1, "instruction counter overflow");
>> - report(status & 2, "branch counter overflow");
>> +
>> + if (pmu_version() > 1) {
>
> Helper? E.g. if this is a "has architectural PMU".
Nit, "intel arch pmu" means "version > 0".
>
>> + // Additionally check that those counters overflowed properly.
>> + status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS);
>> + report(status & 1, "instruction counter overflow");
>> + report(status & 2, "branch counter overflow");
>> + }
>>
>> report_prefix_pop();
>> }
>> @@ -647,12 +674,7 @@ int main(int ac, char **av)
>> buf = malloc(N*64);
>>
>> if (!pmu_version()) {
>> - report_skip("No pmu is detected!");
>> - return report_summary();
>> - }
>> -
>> - if (pmu_version() == 1) {
>> - report_skip("PMU version 1 is not supported.");
>> + report_skip("No Intel Arch PMU is detected!");
>> return report_summary();
>> }
>>
>> --
>> 2.37.2
>>
next prev parent reply other threads:[~2022-10-18 9:33 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-19 11:09 [kvm-unit-tests PATCH v3 00/13] x86/pmu: Test case optimization, fixes and additions Like Xu
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 01/13] x86/pmu: Introduce __start_event() to drop all of the manual zeroing Like Xu
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 02/13] x86/pmu: Introduce multiple_{one, many}() to improve readability Like Xu
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 03/13] x86/pmu: Reset the expected count of the fixed counter 0 when i386 Like Xu
2022-10-05 22:18 ` Sean Christopherson
2022-10-17 7:30 ` Like Xu
2022-10-21 19:16 ` Sean Christopherson
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 04/13] x86/pmu: Add tests for Intel Processor Event Based Sampling (PEBS) Like Xu
2022-10-05 22:21 ` Sean Christopherson
2022-10-05 22:22 ` Sean Christopherson
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 05/13] x86: create pmu group for quick pmu-scope testing Like Xu
2022-10-05 22:23 ` Sean Christopherson
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 06/13] x86/pmu: Test emulation instructions on full-width counters Like Xu
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 07/13] x86/pmu: Pop up FW prefix to avoid out-of-context propagation Like Xu
2022-10-05 22:25 ` Sean Christopherson
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 08/13] x86/pmu: Add PDCM check before accessing PERF_CAP register Like Xu
2022-10-05 22:28 ` Sean Christopherson
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 09/13] x86/pmu: Report SKIP when testing Intel LBR on AMD platforms Like Xu
2022-10-05 22:29 ` Sean Christopherson
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 10/13] x86/pmu: Update testcases to cover Intel Arch PMU Version 1 Like Xu
2022-09-06 7:15 ` Sandipan Das
2022-09-06 13:28 ` Like Xu
2022-09-06 8:16 ` Sandipan Das
2022-09-06 13:35 ` Like Xu
2022-09-08 8:23 ` Sandipan Das
2022-09-19 7:09 ` Like Xu
2022-10-21 7:32 ` Like Xu
2022-10-25 8:34 ` Sandipan Das
2022-10-05 22:35 ` Sean Christopherson
2022-10-18 9:32 ` Like Xu [this message]
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 11/13] x86/pmu: Refine message when testing PMU on AMD platforms Like Xu
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 12/13] x86/pmu: Add assignment framework for Intel-specific HW resources Like Xu
2022-09-06 7:19 ` Sandipan Das
2022-10-05 22:44 ` Sean Christopherson
2022-10-21 7:21 ` Like Xu
2022-10-21 18:22 ` Sean Christopherson
2022-08-19 11:09 ` [kvm-unit-tests PATCH v3 13/13] x86/pmu: Update testcases to cover AMD PMU Like Xu
2022-09-06 7:32 ` Sandipan Das
2022-10-05 22:48 ` Sean Christopherson
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