From: Avi Kivity <avi@redhat.com>
To: Gleb Natapov <gleb@redhat.com>
Cc: Stefan Fritsch <sf@sfritsch.de>,
Jan Kiszka <jan.kiszka@siemens.com>,
kvm@vger.kernel.org
Subject: Re: How to do fast accesses to LAPIC TPR under kvm?
Date: Thu, 18 Oct 2012 14:27:37 +0200 [thread overview]
Message-ID: <507FF5B9.6060605@redhat.com> (raw)
In-Reply-To: <20121018093513.GF20788@redhat.com>
On 10/18/2012 11:35 AM, Gleb Natapov wrote:
> You misunderstood the description. V_INTR_MASKING=1 means that CR8 writes
> are not propagated to real HW APIC.
>
> But KVM does not trap access to CR8 unconditionally. It enables CR8
> intercept only when there is pending interrupt in IRR that cannot be
> immediately delivered due to current TPR value. This should eliminate 99%
> of CR8 intercepts.
>
Right. You will need to expose the alternate encoding of cr8 (IIRC lock
mov reg, cr0) on AMD via cpuid, but otherwise it should just work. Be
aware that this will break cross-vendor migration.
--
error compiling committee.c: too many arguments to function
next prev parent reply other threads:[~2012-10-18 12:27 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-17 19:24 How to do fast accesses to LAPIC TPR under kvm? Stefan Fritsch
2012-10-18 6:13 ` Jan Kiszka
2012-10-18 7:43 ` Stefan Fritsch
2012-10-18 9:35 ` Gleb Natapov
2012-10-18 12:27 ` Avi Kivity [this message]
2012-10-18 17:25 ` Stefan Fritsch
2012-10-19 22:39 ` Stefan Fritsch
2012-10-22 14:10 ` Avi Kivity
2012-10-24 9:19 ` Stefan Fritsch
2012-10-25 13:34 ` Avi Kivity
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