From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: Re: How to do fast accesses to LAPIC TPR under kvm? Date: Thu, 18 Oct 2012 14:27:37 +0200 Message-ID: <507FF5B9.6060605@redhat.com> References: <201210172124.26939.sf@sfritsch.de> <507F9E05.8010508@siemens.com> <20121018093513.GF20788@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: Stefan Fritsch , Jan Kiszka , kvm@vger.kernel.org To: Gleb Natapov Return-path: Received: from mx1.redhat.com ([209.132.183.28]:29800 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754350Ab2JRM1q (ORCPT ); Thu, 18 Oct 2012 08:27:46 -0400 In-Reply-To: <20121018093513.GF20788@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: On 10/18/2012 11:35 AM, Gleb Natapov wrote: > You misunderstood the description. V_INTR_MASKING=1 means that CR8 writes > are not propagated to real HW APIC. > > But KVM does not trap access to CR8 unconditionally. It enables CR8 > intercept only when there is pending interrupt in IRR that cannot be > immediately delivered due to current TPR value. This should eliminate 99% > of CR8 intercepts. > Right. You will need to expose the alternate encoding of cr8 (IIRC lock mov reg, cr0) on AMD via cpuid, but otherwise it should just work. Be aware that this will break cross-vendor migration. -- error compiling committee.c: too many arguments to function