From mboxrd@z Thu Jan  1 00:00:00 1970
From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= <afaerber@suse.de>
Subject: Re: [PATCH V3] target-i386: Enabling IA32_TSC_ADJUST
 for QEMU KVM guest VMs
Date: Tue, 27 Nov 2012 02:51:07 +0100
Message-ID: <50B41C8B.5060302@suse.de>
References: <1353980434.8358.2.camel@WillAuldHomeLinux>
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Cc: "jinsong.liu@intel.com" <jinsong.liu@intel.com>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>, Gleb <gleb@redhat.com>,
	"mtosatti@redhat.com" <mtosatti@redhat.com>,
	Will Auld <will.auld.intel@gmail.com>, qemu-devel <qemu-devel@nongnu.org>,
	"donald.d.dugger@intel.com" <donald.d.dugger@intel.com>,
	"avi@redhat.com" <avi@redhat.com>
To: will.auld@intel.com
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Am 27.11.2012 02:40, schrieb Will Auld:
> CPUID.7.0.EBX[1]=3D1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
>=20
> Basic design is to emulate the MSR by allowing reads and writes to the
> hypervisor vcpu specific locations to store the value of the emulated M=
SRs.
> In this way the IA32_TSC_ADJUST value will be included in all reads to
> the TSC MSR whether through rdmsr or rdtsc.
>=20
> As this is a new MSR that the guest may access and modify its value nee=
ds
> to be migrated along with the other MRSs. The changes here are specific=
ally
> for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added
> for migrating its value.
>=20
> Signed-off-by: Will Auld <will.auld@intel.com>

Something went wrong here, none of the V2 review comments are addressed.
Maybe you sent the wrong patch file?

Cheers,
Andreas

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