From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH 1/2] KVM: nVMX: Clean up and fix pin-based execution controls Date: Wed, 13 Mar 2013 12:48:18 +0100 Message-ID: <51406782.7030300@redhat.com> References: <5140555A.10504@siemens.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: Gleb Natapov , Marcelo Tosatti , kvm , Nadav Har'El , "Nakajima, Jun" To: Jan Kiszka Return-path: Received: from mail-qe0-f45.google.com ([209.85.128.45]:59752 "EHLO mail-qe0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755461Ab3CMLs0 (ORCPT ); Wed, 13 Mar 2013 07:48:26 -0400 Received: by mail-qe0-f45.google.com with SMTP id b4so519783qen.32 for ; Wed, 13 Mar 2013 04:48:25 -0700 (PDT) In-Reply-To: <5140555A.10504@siemens.com> Sender: kvm-owner@vger.kernel.org List-ID: Il 13/03/2013 11:30, Jan Kiszka ha scritto: > Only interrupt and NMI exiting are mandatory for KVM to work, thus can > be exposed to the guest unconditionally, virtual NMI exiting is > optional. So we must not advertise it unless the host supports it. > > Introduce the symbolic constant PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR at > this chance. > > Signed-off-by: Jan Kiszka > --- > arch/x86/include/asm/vmx.h | 2 ++ > arch/x86/kvm/vmx.c | 10 ++++++---- > 2 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h > index e1cc048c..056bda5 100644 > --- a/arch/x86/include/asm/vmx.h > +++ b/arch/x86/include/asm/vmx.h > @@ -71,6 +71,8 @@ > #define PIN_BASED_NMI_EXITING 0x00000008 > #define PIN_BASED_VIRTUAL_NMIS 0x00000020 > > +#define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016 > + > #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000002 > #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 > #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c > index f310bcf..0f0cc6a 100644 > --- a/arch/x86/kvm/vmx.c > +++ b/arch/x86/kvm/vmx.c > @@ -2041,14 +2041,16 @@ static __init void nested_vmx_setup_ctls_msrs(void) > */ > > /* pin-based controls */ > + rdmsr(MSR_IA32_VMX_PINBASED_CTLS, > + nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high); > /* > * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is > * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR. > */ > - nested_vmx_pinbased_ctls_low = 0x16 ; > - nested_vmx_pinbased_ctls_high = 0x16 | > - PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING | > - PIN_BASED_VIRTUAL_NMIS; > + nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; > + nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK | > + PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS; > + nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; > > /* > * Exit controls > Reviewed-by:: Paolo Bonzini