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From: Jan Kiszka <jan.kiszka@web.de>
To: Jun Nakajima <jun.nakajima@intel.com>
Cc: kvm@vger.kernel.org
Subject: Re: [PATCH v2 01/13] nEPT: Support LOAD_IA32_EFER entry/exit controls for L1
Date: Mon, 06 May 2013 09:13:40 +0200	[thread overview]
Message-ID: <51875824.6090402@web.de> (raw)
In-Reply-To: <1367823872-25895-1-git-send-email-jun.nakajima@intel.com>

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On 2013-05-06 09:04, Jun Nakajima wrote:
> Recent KVM, since http://kerneltrap.org/mailarchive/linux-kvm/2010/5/2/6261577
> switch the EFER MSR when EPT is used and the host and guest have different
> NX bits. So if we add support for nested EPT (L1 guest using EPT to run L2)
> and want to be able to run recent KVM as L1, we need to allow L1 to use this
> EFER switching feature.
> 
> To do this EFER switching, KVM uses VM_ENTRY/EXIT_LOAD_IA32_EFER if available,
> and if it isn't, it uses the generic VM_ENTRY/EXIT_MSR_LOAD. This patch adds
> support for the former (the latter is still unsupported).
> 
> Nested entry and exit emulation (prepare_vmcs_02 and load_vmcs12_host_state,
> respectively) already handled VM_ENTRY/EXIT_LOAD_IA32_EFER correctly. So all
> that's left to do in this patch is to properly advertise this feature to L1.
> 
> Note that vmcs12's VM_ENTRY/EXIT_LOAD_IA32_EFER are emulated by L0, by using
> vmx_set_efer (which itself sets one of several vmcs02 fields), so we always
> support this feature, regardless of whether the host supports it.
> 
> Signed-off-by: Nadav Har'El <nyh@il.ibm.com>
> Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
> Signed-off-by: Xinhao Xu <xinhao.xu@intel.com>
> ---
>  arch/x86/kvm/vmx.c | 18 ++++++++++++++----
>  1 file changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 867b810..485ded6 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -2057,6 +2057,7 @@ static __init void nested_vmx_setup_ctls_msrs(void)
>  #else
>  	nested_vmx_exit_ctls_high = 0;
>  #endif
> +	nested_vmx_exit_ctls_high |= VM_EXIT_LOAD_IA32_EFER;

You are using the wrong baseline. This does not apply against next.
Please fix (you can find the properly rebased version in my tree).

Thanks,
Jan



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      parent reply	other threads:[~2013-05-06  7:14 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-05-06  7:04 [PATCH v2 01/13] nEPT: Support LOAD_IA32_EFER entry/exit controls for L1 Jun Nakajima
2013-05-06  7:04 ` [PATCH v2 02/13] nEPT: Move gpte_access() and prefetch_invalid_gpte() to paging_tmpl.h Jun Nakajima
2013-05-06  7:04   ` [PATCH v2 03/13] nEPT: Add EPT tables support " Jun Nakajima
2013-05-06  7:04     ` [PATCH v2 04/13] nEPT: Define EPT-specific link_shadow_page() Jun Nakajima
2013-05-06  7:04       ` [PATCH v2 05/13] nEPT: MMU context for nested EPT Jun Nakajima
2013-05-06  7:04         ` [PATCH v2 06/13] nEPT: Fix cr3 handling in nested exit and entry Jun Nakajima
2013-05-06  7:04           ` [PATCH v2 07/13] nEPT: Fix wrong test in kvm_set_cr3 Jun Nakajima
2013-05-06  7:04             ` [PATCH v2 08/13] nEPT: Some additional comments Jun Nakajima
2013-05-06  7:04               ` [PATCH v2 09/13] nEPT: Advertise EPT to L1 Jun Nakajima
2013-05-06  7:04                 ` [PATCH v2 10/13] nEPT: Nested INVEPT Jun Nakajima
2013-05-06  7:04                   ` [PATCH v2 11/13] nEPT: Miscelleneous cleanups Jun Nakajima
2013-05-06  7:04                     ` [PATCH v2 12/13] nEPT: Move is_rsvd_bits_set() to paging_tmpl.h Jun Nakajima
2013-05-06  7:04                       ` [PATCH v2 13/13] nEPT: Inject EPT violation/misconfigration Jun Nakajima
2013-05-06  7:13 ` Jan Kiszka [this message]

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