From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Daney Subject: Re: [PATCH 00/18] KVM/MIPS32: Support for the new Virtualization ASE (VZ-ASE) Date: Mon, 20 May 2013 11:58:17 -0700 Message-ID: <519A7249.1030302@gmail.com> References: <1368942460-15577-1-git-send-email-sanjayl@kymasys.com> <519A4640.6060202@gmail.com> <456B70C6-A896-4B94-B8EF-DE6ED26CE859@kymasys.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: Sanjay Lal , kvm@vger.kernel.org, linux-mips@linux-mips.org, Ralf Baechle , Gleb Natapov , Marcelo Tosatti To: "Maciej W. Rozycki" Return-path: Received: from mail-da0-f44.google.com ([209.85.210.44]:35713 "EHLO mail-da0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756068Ab3ETS6U (ORCPT ); Mon, 20 May 2013 14:58:20 -0400 Received: by mail-da0-f44.google.com with SMTP id z8so4102174daj.17 for ; Mon, 20 May 2013 11:58:20 -0700 (PDT) In-Reply-To: Sender: kvm-owner@vger.kernel.org List-ID: On 05/20/2013 11:36 AM, Maciej W. Rozycki wrote: > On Mon, 20 May 2013, Sanjay Lal wrote: > >> (1) Newer versions of the MIPS architecture define scratch registers for >> just this purpose, but since we have to support standard MIPS32R2 >> processors, we use the DDataLo Register (CP0 Register 28, Select 3) as a >> scratch register to save k0 and save k1 @ a known offset from EBASE. > > That's rather risky as the implementation of this register (and its > presence in the first place) is processor-specific. Do you maintain a > list of PRId values the use of this register is safe with? > FWIW: The MIPS-VZ architecture module requires the presence of CP0 scratch registers that can be used for this in the exception handlers without having to worry about using these implementation dependent registers. For the trap-and-emulate only version, there really is no choice other than to re-purpose some of the existing CP0 registers. David Daney