From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [RFC PATCH v2 2/2] add support for Hyper-V invariant TSC Date: Thu, 23 May 2013 18:44:50 +0200 Message-ID: <519E4782.3020402@redhat.com> References: <1368947197-9033-1-git-send-email-vrozenfe@redhat.com> <1368947197-9033-3-git-send-email-vrozenfe@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: kvm@vger.kernel.org, gleb@redhat.com, mtosatti@redhat.com, pl@dlh.net To: Vadim Rozenfeld Return-path: Received: from mail-ye0-f181.google.com ([209.85.213.181]:35521 "EHLO mail-ye0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758976Ab3EWQpC (ORCPT ); Thu, 23 May 2013 12:45:02 -0400 Received: by mail-ye0-f181.google.com with SMTP id r10so3981yen.12 for ; Thu, 23 May 2013 09:45:01 -0700 (PDT) In-Reply-To: <1368947197-9033-3-git-send-email-vrozenfe@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: Il 19/05/2013 09:06, Vadim Rozenfeld ha scritto: > The following patch allows to activate a partition reference > time enlightenment that is based on the host platform's support > for an Invariant Time Stamp Counter (iTSC). > NOTE: This code will survive migration due to lack of VM stop/resume > handlers, when offset, scale and sequence should be > readjusted. > > --- > arch/x86/kvm/x86.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index 9645dab..b423fe4 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -1838,7 +1838,6 @@ static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) > u64 gfn; > unsigned long addr; > HV_REFERENCE_TSC_PAGE tsc_ref; > - tsc_ref.TscSequence = 0; > if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) { > kvm->arch.hv_tsc_page = data; > break; > @@ -1848,6 +1847,11 @@ static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) > HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT); > if (kvm_is_error_hva(addr)) > return 1; > + tsc_ref.TscSequence = > + boot_cpu_has(X86_FEATURE_CONSTANT_TSC) ? 1 : 0; Thinking more of migration, could we increment whatever sequence value we found (or better, do (x|3)+2 to skip over 0 and 0xFFFFFFFF), instead of forcing it to 1? Add HV_X64_MSR_REFERENCE_TSC to msrs_to_save, and migration should just work. Paolo > + tsc_ref.TscScale = > + ((10000LL << 32) / vcpu->arch.virtual_tsc_khz) << 32; > + tsc_ref.TscOffset = 0; > if (__copy_to_user((void __user *)addr, &tsc_ref, sizeof(tsc_ref))) > return 1; > mark_page_dirty(kvm, gfn); >