From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jan Kiszka Subject: Re: [PATCH 2/4] kvm-unit-tests: VMX: Add test cases for CR0/4 shadowing Date: Thu, 15 Aug 2013 10:07:22 +0200 Message-ID: <520C8C3A.50308@web.de> References: <1376409368-7016-1-git-send-email-yzt356@gmail.com> <1376409368-7016-3-git-send-email-yzt356@gmail.com> <520C837E.7030407@web.de> <520C879B.30908@web.de> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="0aL6rJtTdsDFpoNUfcKfJv2mUgdoFnuRg" Cc: kvm , Gleb Natapov , Paolo Bonzini To: Arthur Chunqi Li Return-path: Received: from mout.web.de ([212.227.17.11]:64713 "EHLO mout.web.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751780Ab3HOIHY (ORCPT ); Thu, 15 Aug 2013 04:07:24 -0400 Received: from mchn199C.mchp.siemens.de ([95.157.58.223]) by smtp.web.de (mrweb102) with ESMTPSA (Nemesis) id 0MFL6u-1VM1ew1wge-00EKQX for ; Thu, 15 Aug 2013 10:07:22 +0200 In-Reply-To: Sender: kvm-owner@vger.kernel.org List-ID: This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --0aL6rJtTdsDFpoNUfcKfJv2mUgdoFnuRg Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 2013-08-15 09:59, Arthur Chunqi Li wrote: > On Thu, Aug 15, 2013 at 3:47 PM, Jan Kiszka wrote: >> On 2013-08-15 09:40, Arthur Chunqi Li wrote: >>> On Thu, Aug 15, 2013 at 3:30 PM, Jan Kiszka wrote= : >>>> On 2013-08-13 17:56, Arthur Chunqi Li wrote: >>>>> Add testing for CR0/4 shadowing. >>>> >>>> A few sentences on the test strategy would be good. >>>> >>>>> >>>>> Signed-off-by: Arthur Chunqi Li >>>>> --- >>>>> lib/x86/vm.h | 4 + >>>>> x86/vmx_tests.c | 218 +++++++++++++++++++++++++++++++++++++++++++= ++++++++++++ >>>>> 2 files changed, 222 insertions(+) >>>>> >>>>> diff --git a/lib/x86/vm.h b/lib/x86/vm.h >>>>> index eff6f72..6e0ce2b 100644 >>>>> --- a/lib/x86/vm.h >>>>> +++ b/lib/x86/vm.h >>>>> @@ -17,9 +17,13 @@ >>>>> #define PTE_ADDR (0xffffffffff000ull) >>>>> >>>>> #define X86_CR0_PE 0x00000001 >>>>> +#define X86_CR0_MP 0x00000002 >>>>> +#define X86_CR0_TS 0x00000008 >>>>> #define X86_CR0_WP 0x00010000 >>>>> #define X86_CR0_PG 0x80000000 >>>>> #define X86_CR4_VMXE 0x00000001 >>>>> +#define X86_CR4_TSD 0x00000004 >>>>> +#define X86_CR4_DE 0x00000008 >>>>> #define X86_CR4_PSE 0x00000010 >>>>> #define X86_CR4_PAE 0x00000020 >>>>> #define X86_CR4_PCIDE 0x00020000 >>>>> diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c >>>>> index 61b0cef..44be3f4 100644 >>>>> --- a/x86/vmx_tests.c >>>>> +++ b/x86/vmx_tests.c >>>>> @@ -5,12 +5,18 @@ >>>>> >>>>> u64 ia32_pat; >>>>> u64 ia32_efer; >>>>> +u32 stage; >>>>> >>>>> static inline void vmcall() >>>>> { >>>>> asm volatile("vmcall"); >>>>> } >>>>> >>>>> +static inline void set_stage(u32 s) >>>>> +{ >>>>> + asm volatile("mov %0, stage\n\t"::"r"(s):"memory", "cc"); >>>>> +} >>>>> + >>>> >>>> Why do we need "state =3D s" as assembler instruction? >>> This is due to assembler optimization. If we simply use "state =3D s"= , >>> assembler will sometimes optimize it and state may not be set indeed.= >> >> volatile u32 stage? And we have barrier() to avoid reordering. > Reordering here is not a big deal here, though it is actually needed > here. I occurred the following problem: >=20 > stage =3D 1; > do something that causes vmexit; > stage =3D 2; >=20 > Then the compiler will optimize "stage =3D 1" and "stage =3D 2" to one > instruction "stage =3D2", since instructions between them don't use > "stage". Can volatile solve this problem? Yep. Jan --0aL6rJtTdsDFpoNUfcKfJv2mUgdoFnuRg Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.16 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iEYEARECAAYFAlIMjDoACgkQitSsb3rl5xRM2QCeJeIBoj8asnWEuFQDCygG2R88 UqsAoMrkt79BmGhc6o9/6HRLEz3WNAyM =k9A4 -----END PGP SIGNATURE----- --0aL6rJtTdsDFpoNUfcKfJv2mUgdoFnuRg--