From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH V3] target-i386: forward CPUID cache leaves when -cpu host is used Date: Thu, 19 Sep 2013 19:33:49 +0200 Message-ID: <523B357D.8090506@redhat.com> References: <1378134397-16547-1-git-send-email-benoit@irqsave.net> <1378134397-16547-2-git-send-email-benoit@irqsave.net> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: qemu-devel@nongnu.org, imammedo@redhat.com, afaerber@suse.de, kvm@vger.kernel.org, ehabkost@redhat.com To: =?ISO-8859-1?Q?Beno=EEt_Canet?= Return-path: Received: from mail-yh0-f49.google.com ([209.85.213.49]:48512 "EHLO mail-yh0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752015Ab3ISRdk (ORCPT ); Thu, 19 Sep 2013 13:33:40 -0400 Received: by mail-yh0-f49.google.com with SMTP id i57so4171974yha.8 for ; Thu, 19 Sep 2013 10:33:39 -0700 (PDT) In-Reply-To: <1378134397-16547-2-git-send-email-benoit@irqsave.net> Sender: kvm-owner@vger.kernel.org List-ID: Il 02/09/2013 17:06, Beno=EEt Canet ha scritto: > Some users running cpu intensive tasks checking the cache CPUID leave= s at > startup and making decisions based on the result reported that the gu= est was > not reflecting the host CPUID leaves when -cpu host is used. >=20 > This patch fix this. >=20 > Signed-off-by: Benoit Canet > --- > target-i386/cpu-qom.h | 3 +++ > target-i386/cpu.c | 19 +++++++++++++++++++ > 2 files changed, 22 insertions(+) >=20 > diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h > index c4447c2..b1d1bd8 100644 > --- a/target-i386/cpu-qom.h > +++ b/target-i386/cpu-qom.h > @@ -70,6 +70,9 @@ typedef struct X86CPU { > bool hyperv_relaxed_timing; > int hyperv_spinlock_attempts; > =20 > + /* if true the CPUID code directly forward host cache leaves to = the guest */ > + bool fwd_host_cache_info; > + > /* Features that were filtered out because of missing host capab= ilities */ > uint32_t filtered_features[FEATURE_WORDS]; > =20 > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index c36345e..f0df4db 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -486,6 +486,7 @@ typedef struct x86_def_t { > int stepping; > FeatureWordArray features; > char model_id[48]; > + bool fwd_host_cache_info; > } x86_def_t; > =20 > #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) > @@ -1139,6 +1140,7 @@ static void kvm_cpu_fill_host(x86_def_t *x86_cp= u_def) > assert(kvm_enabled()); > =20 > x86_cpu_def->name =3D "host"; > + x86_cpu_def->fwd_host_cache_info =3D true; > host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); > x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx); > =20 > @@ -1888,6 +1890,7 @@ static void cpu_x86_register(X86CPU *cpu, const= char *name, Error **errp) > env->features[FEAT_C000_0001_EDX] =3D def->features[FEAT_C000_00= 01_EDX]; > env->features[FEAT_7_0_EBX] =3D def->features[FEAT_7_0_EBX]; > env->cpuid_xlevel2 =3D def->xlevel2; > + cpu->fwd_host_cache_info =3D def->fwd_host_cache_info; > =20 > object_property_set_str(OBJECT(cpu), def->model_id, "model-id", = errp); > } > @@ -2062,6 +2065,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t = index, uint32_t count, > break; > case 2: > /* cache info: needed for Pentium Pro compatibility */ > + if (cpu->fwd_host_cache_info) { > + host_cpuid(index, 0, eax, ebx, ecx, edx); > + break; > + } > *eax =3D 1; /* Number of CPUID[EAX=3D2] calls required */ > *ebx =3D 0; > *ecx =3D 0; > @@ -2071,6 +2078,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t = index, uint32_t count, > break; > case 4: > /* cache info: needed for Core compatibility */ > + if (cpu->fwd_host_cache_info) { > + host_cpuid(index, count, eax, ebx, ecx, edx); > + break; > + } > if (cs->nr_cores > 1) { > *eax =3D (cs->nr_cores - 1) << 26; > } else { > @@ -2228,6 +2239,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t = index, uint32_t count, > break; > case 0x80000005: > /* cache info (L1 cache) */ > + if (cpu->fwd_host_cache_info) { > + host_cpuid(index, 0, eax, ebx, ecx, edx); > + break; > + } > *eax =3D (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 1= 6) | \ > (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); > *ebx =3D (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 1= 6) | \ > @@ -2239,6 +2254,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t = index, uint32_t count, > break; > case 0x80000006: > /* cache info (L2 cache) */ > + if (cpu->fwd_host_cache_info) { > + host_cpuid(index, 0, eax, ebx, ecx, edx); > + break; > + } > *eax =3D (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \ > (L2_DTLB_2M_ENTRIES << 16) | \ > (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \ >=20 I renamed the new field to cache_info_passthrough (Eduardo had a "pmu_passthrough" patch a few weeks ago) and will push it tomorrow to uq/master. Thanks, Paolo