From: "Rémi Denis-Courmont" <remi@remlab.net>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>,
Andy Chiu <andy.chiu@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
Guo Ren <guoren@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
Andy Chiu <andy.chiu@sifive.com>
Subject: Re: [PATCH -next v21 09/27] riscv: Introduce struct/helpers to save/restore per-task Vector state
Date: Mon, 12 Jun 2023 17:32:40 +0300 [thread overview]
Message-ID: <5271851.rBgCu3BfMA@basile.remlab.net> (raw)
In-Reply-To: <20230605110724.21391-10-andy.chiu@sifive.com>
Le maanantaina 5. kesäkuuta 2023, 14.07.06 EEST Andy Chiu a écrit :
> @@ -32,13 +54,86 @@ static __always_inline void riscv_v_disable(void)
> csr_clear(CSR_SSTATUS, SR_VS);
> }
>
> +static __always_inline void __vstate_csr_save(struct __riscv_v_ext_state
> *dest) +{
> + asm volatile (
> + "csrr %0, " __stringify(CSR_VSTART) "\n\t"
> + "csrr %1, " __stringify(CSR_VTYPE) "\n\t"
> + "csrr %2, " __stringify(CSR_VL) "\n\t"
> + "csrr %3, " __stringify(CSR_VCSR) "\n\t"
> + : "=r" (dest->vstart), "=r" (dest->vtype), "=r" (dest-
>vl),
> + "=r" (dest->vcsr) : :);
> +}
> +
> +static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state
> *src) +{
> + asm volatile (
> + ".option push\n\t"
> + ".option arch, +v\n\t"
> + "vsetvl x0, %2, %1\n\t"
> + ".option pop\n\t"
> + "csrw " __stringify(CSR_VSTART) ", %0\n\t"
> + "csrw " __stringify(CSR_VCSR) ", %3\n\t"
> + : : "r" (src->vstart), "r" (src->vtype), "r" (src->vl),
> + "r" (src->vcsr) :);
> +}
> +
> +static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state
> *save_to, + void *datap)
> +{
> + unsigned long vl;
> +
> + riscv_v_enable();
> + __vstate_csr_save(save_to);
> + asm volatile (
> + ".option push\n\t"
> + ".option arch, +v\n\t"
> + "vsetvli %0, x0, e8, m8, ta, ma\n\t"
> + "vse8.v v0, (%1)\n\t"
> + "add %1, %1, %0\n\t"
> + "vse8.v v8, (%1)\n\t"
> + "add %1, %1, %0\n\t"
> + "vse8.v v16, (%1)\n\t"
> + "add %1, %1, %0\n\t"
> + "vse8.v v24, (%1)\n\t"
> + ".option pop\n\t"
> + : "=&r" (vl) : "r" (datap) : "memory");
> + riscv_v_disable();
> +}
Shouldn't this use `vs8r.v` rather than `vse8.v`, and do away with `vsetvli`?
This seems like a textbook use case for the whole-register store instruction,
no?
> +
> +static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state
> *restore_from, + void
*datap)
> +{
> + unsigned long vl;
> +
> + riscv_v_enable();
> + asm volatile (
> + ".option push\n\t"
> + ".option arch, +v\n\t"
> + "vsetvli %0, x0, e8, m8, ta, ma\n\t"
> + "vle8.v v0, (%1)\n\t"
> + "add %1, %1, %0\n\t"
> + "vle8.v v8, (%1)\n\t"
> + "add %1, %1, %0\n\t"
> + "vle8.v v16, (%1)\n\t"
> + "add %1, %1, %0\n\t"
> + "vle8.v v24, (%1)\n\t"
> + ".option pop\n\t"
> + : "=&r" (vl) : "r" (datap) : "memory");
> + __vstate_csr_restore(restore_from);
> + riscv_v_disable();
> +}
> +
Ditto but `vl8r.v`.
> #else /* ! CONFIG_RISCV_ISA_V */
>
> struct pt_regs;
>
> static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; }
> static __always_inline bool has_vector(void) { return false; }
> +static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return
> false; } #define riscv_v_vsize (0)
> +#define riscv_v_vstate_off(regs) do {} while (0)
> +#define riscv_v_vstate_on(regs) do {} while (0)
>
> #endif /* CONFIG_RISCV_ISA_V */
>
--
Реми Дёни-Курмон
http://www.remlab.net/
next prev parent reply other threads:[~2023-06-12 14:42 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-05 11:06 [PATCH -next v21 00/27] riscv: Add vector ISA support Andy Chiu
2023-06-05 11:06 ` [PATCH -next v21 01/27] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-06-05 11:06 ` [PATCH -next v21 02/27] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 03/27] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 Andy Chiu
2023-06-08 12:36 ` Heiko Stübner
2023-06-28 0:30 ` Stefan O'Rear
2023-06-28 1:56 ` Palmer Dabbelt
2023-06-28 4:53 ` Stefan O'Rear
2023-06-05 11:07 ` [PATCH -next v21 04/27] riscv: Add new csr defines related to vector extension Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 05/27] riscv: Clear vector regfile on bootup Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 06/27] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 07/27] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 08/27] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 09/27] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-06-12 14:32 ` Rémi Denis-Courmont [this message]
2023-06-13 14:19 ` Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 10/27] riscv: Add task switch support for vector Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 11/27] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-06-05 16:04 ` Conor Dooley
2023-06-08 13:58 ` Heiko Stübner
2023-06-05 11:07 ` [PATCH -next v21 12/27] riscv: Add ptrace vector support Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 13/27] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 14/27] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-10-08 9:19 ` Aurelien Jarno
2023-10-08 16:23 ` Andy Chiu
2023-10-09 17:08 ` Aurelien Jarno
2023-06-05 11:07 ` [PATCH -next v21 15/27] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 16/27] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 17/27] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 18/27] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 19/27] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 20/27] riscv: hwcap: change ELF_HWCAP to a function Andy Chiu
2023-06-05 16:24 ` Conor Dooley
2023-06-05 11:07 ` [PATCH -next v21 21/27] riscv: Add prctl controls for userspace vector management Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 22/27] riscv: Add sysctl to set the default vector rule for new processes Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 23/27] riscv: detect assembler support for .option arch Andy Chiu
2023-06-05 15:48 ` Nathan Chancellor
2023-06-05 16:25 ` Conor Dooley
2024-01-21 1:13 ` Eric Biggers
2024-01-21 2:55 ` Palmer Dabbelt
2024-01-21 14:32 ` Andy Chiu
2024-01-21 18:10 ` Eric Biggers
2024-01-22 22:29 ` Nathan Chancellor
2024-01-24 21:58 ` Eric Biggers
2023-06-05 11:07 ` [PATCH -next v21 24/27] riscv: Enable Vector code to be built Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 25/27] riscv: Add documentation for Vector Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 26/27] selftests: Test RISC-V Vector prctl interface Andy Chiu
2023-06-05 11:07 ` [PATCH -next v21 27/27] selftests: add .gitignore file for RISC-V hwprobe Andy Chiu
2023-06-09 14:00 ` [PATCH -next v21 00/27] riscv: Add vector ISA support Palmer Dabbelt
2023-06-09 14:50 ` patchwork-bot+linux-riscv
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