From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [Qemu-devel] [RFC] create a single workqueue for each vm to update vm irq routing table Date: Thu, 28 Nov 2013 10:29:36 +0100 Message-ID: <52970D00.9060109@redhat.com> References: <52949847.6020908@redhat.com> <5294A68F.6060301@redhat.com> <5294B461.5000405@redhat.com> <5294B634.4050801@cloudius-systems.com> <20131126150357.GA20352@redhat.com> <5294BC3B.6070902@redhat.com> <5297050E.6000700@redhat.com> <20131128091903.GA4609@kernel.org> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: "Zhanghaoyu (A)" , Gleb Natapov , Avi Kivity , Avi Kivity , "Huangweidong (C)" , KVM , "Michael S. Tsirkin" , "Jinxin (F)" , Luonengjun , "qemu-devel@nongnu.org" , Zanghongyong To: Gleb Natapov Return-path: Received: from mx1.redhat.com ([209.132.183.28]:34255 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751271Ab3K1J3v (ORCPT ); Thu, 28 Nov 2013 04:29:51 -0500 In-Reply-To: <20131128091903.GA4609@kernel.org> Sender: kvm-owner@vger.kernel.org List-ID: Il 28/11/2013 10:19, Gleb Natapov ha scritto: > Not changing current behaviour is certainly safer, but I am still not 100% > convinced we have to ensure this. > > Suppose guest does: > > 1: change msi interrupt by writing to pci register > 2: read the pci register to flush the write > 3: zero idt > > I am pretty certain that this code can get interrupt after step 2 on real HW, > but I cannot tell if guest can rely on it to be delivered exactly after > read instruction or it can be delayed by couple of instructions. I agree it's fragile, but if a dedicated SRCU can meet the requirements (possibly with synchronize_srcu_expedited), I prefer not to break it. Paolo Seems to me > it would be fragile for an OS to depend on this behaviour. AFAIK Linux does not.