From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH] KVM: nVMX: Support direct APIC access from L2 Date: Wed, 18 Dec 2013 10:27:31 +0100 Message-ID: <52B16A83.6050402@redhat.com> References: <52AEEA42.7020608@siemens.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: Gleb Natapov , kvm To: Jan Kiszka Return-path: Received: from mail-ee0-f42.google.com ([74.125.83.42]:44735 "EHLO mail-ee0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751588Ab3LRJ1e (ORCPT ); Wed, 18 Dec 2013 04:27:34 -0500 Received: by mail-ee0-f42.google.com with SMTP id e53so3408917eek.1 for ; Wed, 18 Dec 2013 01:27:33 -0800 (PST) In-Reply-To: <52AEEA42.7020608@siemens.com> Sender: kvm-owner@vger.kernel.org List-ID: Il 16/12/2013 12:55, Jan Kiszka ha scritto: > It's a pathological case, but still a valid one: If L1 disables APIC > virtualization and also allows L2 to directly write to the APIC page, we > have to forcibly enable APIC virtualization while in L2 if the in-kernel > APIC is in use. > > This allows to run the direct interrupt test case in the vmx unit test > without x2APIC. > > Signed-off-by: Jan Kiszka > --- > arch/x86/kvm/vmx.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c > index da04247..7c3ea63 100644 > --- a/arch/x86/kvm/vmx.c > +++ b/arch/x86/kvm/vmx.c > @@ -7771,6 +7771,11 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) > else > vmcs_write64(APIC_ACCESS_ADDR, > page_to_phys(vmx->nested.apic_access_page)); > + } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) { > + exec_control |= > + SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; > + vmcs_write64(APIC_ACCESS_ADDR, > + page_to_phys(vcpu->kvm->arch.apic_access_page)); > } > > vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); > Applied, thanks. Paolo