From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Daney Subject: Re: [PATCH 04/21] MIPS: KVM: Fix CP0_EBASE KVM register id Date: Fri, 25 Apr 2014 09:36:50 -0700 Message-ID: <535A8F22.4090402@caviumnetworks.com> References: <1398439204-26171-1-git-send-email-james.hogan@imgtec.com> <1398439204-26171-5-git-send-email-james.hogan@imgtec.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Paolo Bonzini , Gleb Natapov , , Ralf Baechle , , David Daney , Sanjay Lal To: James Hogan Return-path: Received: from mail-bn1blp0181.outbound.protection.outlook.com ([207.46.163.181]:19881 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752134AbaDYQg4 (ORCPT ); Fri, 25 Apr 2014 12:36:56 -0400 In-Reply-To: <1398439204-26171-5-git-send-email-james.hogan@imgtec.com> Sender: kvm-owner@vger.kernel.org List-ID: On 04/25/2014 08:19 AM, James Hogan wrote: > KVM_REG_MIPS_CP0_EBASE is defined as 64bit, but is a 32bit register e= ven > in MIPS64, so fix the definition. > > Note, this definition isn't actually used yet, so it didn't cause any > problems. > > Signed-off-by: James Hogan > Cc: Paolo Bonzini > Cc: Gleb Natapov > Cc: kvm@vger.kernel.org > Cc: Ralf Baechle > Cc: linux-mips@linux-mips.org > Cc: David Daney > Cc: Sanjay Lal > --- > arch/mips/kvm/kvm_mips.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c > index 14511138f187..46cea0bad518 100644 > --- a/arch/mips/kvm/kvm_mips.c > +++ b/arch/mips/kvm/kvm_mips.c > @@ -512,7 +512,7 @@ kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *= vcpu, > #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) > #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) > #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) > -#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) > +#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_32(15, 1) According to: MIPS=AE Architecture Reference Manual Volume III: The MIPS64=AE and microMIPS64TM Privileged Resource Architecture Document Number: MD00089 Revision 5.02 April 30, 2013 In section 9.39 EBase Register (CP0 Register 15, Select 1), we see that= =20 EBase can be either 32-bits or 64-bits wide. I would recommend leaving this as a 64-bit wide register, so that CPU=20 implementations with the wider EBase can be supported. Alternately, probe for the width and use the appropriate 32-bit or=20 64-bit to more closely reflect reality. > #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) > #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) > #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) >