From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Daney Subject: Re: [PATCH 05/21] MIPS: KVM: Add CP0_EPC KVM register access Date: Fri, 25 Apr 2014 14:45:07 -0700 Message-ID: <535AD763.1040604@gmail.com> References: <1398439204-26171-1-git-send-email-james.hogan@imgtec.com> <1398439204-26171-6-git-send-email-james.hogan@imgtec.com> <535A90E1.2030705@gmail.com> <10468933.5AvfRZXSN7@radagast> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: linux-mips@linux-mips.org, Paolo Bonzini , Gleb Natapov , kvm@vger.kernel.org, Ralf Baechle , David Daney , Sanjay Lal To: James Hogan Return-path: Received: from mail-ie0-f173.google.com ([209.85.223.173]:37812 "EHLO mail-ie0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751139AbaDYVpJ (ORCPT ); Fri, 25 Apr 2014 17:45:09 -0400 Received: by mail-ie0-f173.google.com with SMTP id rl12so4431504iec.18 for ; Fri, 25 Apr 2014 14:45:09 -0700 (PDT) In-Reply-To: <10468933.5AvfRZXSN7@radagast> Sender: kvm-owner@vger.kernel.org List-ID: On 04/25/2014 01:29 PM, James Hogan wrote: > Hi David, > > On Friday 25 April 2014 09:44:17 David Daney wrote: >> On 04/25/2014 08:19 AM, James Hogan wrote: >>> Contrary to the comment, the guest CP0_EPC register cannot be set via >>> kvm_regs, since it is distinct from the guest PC. Add the EPC register >>> to the KVM_{GET,SET}_ONE_REG ioctl interface. >>> >>> Signed-off-by: James Hogan >>> Cc: Paolo Bonzini >>> Cc: Gleb Natapov >>> Cc: kvm@vger.kernel.org >>> Cc: Ralf Baechle >>> Cc: linux-mips@linux-mips.org >>> Cc: David Daney >>> Cc: Sanjay Lal >> >> NACK... >> >>> --- >>> >>> arch/mips/kvm/kvm_mips.c | 9 ++++++++- >>> 1 file changed, 8 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c >>> index 46cea0bad518..db41876cbac5 100644 >>> --- a/arch/mips/kvm/kvm_mips.c >>> +++ b/arch/mips/kvm/kvm_mips.c >>> @@ -512,6 +512,7 @@ kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, >>> >>> #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) >>> #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) >>> #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) >>> >>> +#define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) >> >> This is already called KVM_REG_MIPS_PC, you cannot change that. > > KVM_REG_MIPS_PC gets you vcpu->arch.pc, i.e. the next address of guest > execution. > > KVM_REG_MIPS_CP0_EPC gets you the guest's CP0 EPC register which is the PC of > the last guest exception. > > They are quite distinct state, even though vcpu->arch.pc is read from the > *root context*'s CP0 EPC register after an exception or interrupt. > Sorry, my mistake. I was confusing Root/Host and Guest state. I remove my objection. David Daney > Cheers > James > >> >>> #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_32(15, 1) >>> #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) >>> #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) >>> >>> @@ -567,7 +568,7 @@ static u64 kvm_mips_get_one_regs[] = { >>> >>> KVM_REG_MIPS_CP0_ENTRYHI, >>> KVM_REG_MIPS_CP0_STATUS, >>> KVM_REG_MIPS_CP0_CAUSE, >>> >>> - /* EPC set via kvm_regs, et al. */ >>> + KVM_REG_MIPS_CP0_EPC, >>> >>> KVM_REG_MIPS_CP0_CONFIG, >>> KVM_REG_MIPS_CP0_CONFIG1, >>> KVM_REG_MIPS_CP0_CONFIG2, >>> >>> @@ -620,6 +621,9 @@ static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, >>> >>> case KVM_REG_MIPS_CP0_CAUSE: >>> v = (long)kvm_read_c0_guest_cause(cop0); >>> break; >>> >>> + case KVM_REG_MIPS_CP0_EPC: >>> + v = (long)kvm_read_c0_guest_epc(cop0); >>> + break; >>> >>> case KVM_REG_MIPS_CP0_ERROREPC: >>> v = (long)kvm_read_c0_guest_errorepc(cop0); >>> break; >>> >>> @@ -716,6 +720,9 @@ static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, >>> >>> case KVM_REG_MIPS_CP0_CAUSE: >>> kvm_write_c0_guest_cause(cop0, v); >>> break; >>> >>> + case KVM_REG_MIPS_CP0_EPC: >>> + kvm_write_c0_guest_epc(cop0, v); >>> + break; >>> >>> case KVM_REG_MIPS_CP0_ERROREPC: >>> kvm_write_c0_guest_errorepc(cop0, v); >>> break;