From: Alexander Graf <agraf@suse.de>
To: Paul Mackerras <paulus@samba.org>
Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs
Date: Fri, 02 May 2014 10:35:09 +0200 [thread overview]
Message-ID: <536358BD.9030304@suse.de> (raw)
In-Reply-To: <20140430221259.GD9671@iris.ozlabs.ibm.com>
On 05/01/2014 12:12 AM, Paul Mackerras wrote:
> On Tue, Apr 29, 2014 at 06:17:37PM +0200, Alexander Graf wrote:
>> When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs
>> that we don't emulate. Just ignore accesses to them.
>>
>> Signed-off-by: Alexander Graf <agraf@suse.de>
> This patch is OK as it stands, but in fact the architecture says that
> kernel accesses to unimplemented SPRs are mostly supposed to be no-ops
> rather than causing a trap (mostly == excluding mtspr to 0 or mfspr
> from 0, 4, 5 or 6). I have a patch to implement that, which I'll
> post.
I think what we want is a flag similar to x86 where we can force ignore
unknown SPRs, but leave it at triggering an interrupt as default. We
usually have to be at least aware of unknown SPRs and check that not
implementing them is ok for the guest.
Debugging a program interrupt because of an unknown SPR is usually a lot
easier than debugging a breaking guest because it was using the SPR as
storage and we didn't back it by anything.
Alex
next prev parent reply other threads:[~2014-05-02 8:35 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-29 16:17 [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support Alexander Graf
2014-04-29 16:17 ` [PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs Alexander Graf
2014-04-30 22:12 ` Paul Mackerras
2014-05-02 8:35 ` Alexander Graf [this message]
2014-05-07 7:09 ` Paul Mackerras
2014-05-08 12:11 ` Alexander Graf
2014-04-29 16:17 ` [PATCH 2/6] KVM: PPC: Book3S PR: Emulate TIR register Alexander Graf
2014-04-30 5:51 ` Michael Neuling
2014-04-30 10:06 ` Alexander Graf
2014-04-29 16:17 ` [PATCH 3/6] KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR Alexander Graf
2014-04-29 16:17 ` [PATCH 4/6] KVM: PPC: Book3S PR: Expose TAR facility to guest Alexander Graf
2014-04-29 16:17 ` [PATCH 5/6] KVM: PPC: Book3S PR: Expose EBB registers Alexander Graf
2014-04-29 16:17 ` [PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers Alexander Graf
2014-05-17 6:20 ` Paul Mackerras
2014-05-19 13:09 ` Alexander Graf
2014-05-20 9:59 ` Paul Mackerras
2014-05-20 11:49 ` Alexander Graf
2014-05-04 16:36 ` [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support Aneesh Kumar K.V
2014-05-05 11:18 ` Alexander Graf
2014-05-05 14:38 ` Aneesh Kumar K.V
2014-05-05 14:42 ` Alexander Graf
2014-05-05 14:48 ` Aneesh Kumar K.V
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