[PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support

[PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support

[Alexander Graf]

When running on a POWER8 host, we get away with running the guest as POWER7
and nothing falls apart.

However, when we start exposing POWER8 as guest CPU, guests will start using
new abilities on POWER8 which we need to handle.

This patch set does a minimalistic approach to implementing those bits to
make guests happy enough to run.


Alex

Alexander Graf (6):
  KVM: PPC: Book3S PR: Ignore PMU SPRs
  KVM: PPC: Book3S PR: Emulate TIR register
  KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR
  KVM: PPC: Book3S PR: Expose TAR facility to guest
  KVM: PPC: Book3S PR: Expose EBB registers
  KVM: PPC: Book3S PR: Expose TM registers

 arch/powerpc/include/asm/kvm_asm.h        | 18 ++++---
 arch/powerpc/include/asm/kvm_book3s_asm.h |  2 +
 arch/powerpc/include/asm/kvm_host.h       |  3 ++
 arch/powerpc/kernel/asm-offsets.c         |  3 ++
 arch/powerpc/kvm/book3s.c                 | 34 +++++++++++++
 arch/powerpc/kvm/book3s_emulate.c         | 53 ++++++++++++++++++++
 arch/powerpc/kvm/book3s_hv.c              | 30 -----------
 arch/powerpc/kvm/book3s_pr.c              | 82 +++++++++++++++++++++++++++++++
 arch/powerpc/kvm/book3s_segment.S         | 25 ++++++++++
 9 files changed, 212 insertions(+), 38 deletions(-)

-- 
1.8.1.4

[PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs

[Alexander Graf]

When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs
that we don't emulate. Just ignore accesses to them.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 arch/powerpc/kvm/book3s_emulate.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 45d0a80..914beb2 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -455,6 +455,11 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
 	case SPRN_WPAR_GEKKO:
 	case SPRN_MSSSR0:
 	case SPRN_DABR:
+	case SPRN_MMCRS:
+	case SPRN_MMCRA:
+	case SPRN_MMCR0:
+	case SPRN_MMCR1:
+	case SPRN_MMCR2:
 		break;
 unprivileged:
 	default:
@@ -553,6 +558,11 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
 	case SPRN_WPAR_GEKKO:
 	case SPRN_MSSSR0:
 	case SPRN_DABR:
+	case SPRN_MMCRS:
+	case SPRN_MMCRA:
+	case SPRN_MMCR0:
+	case SPRN_MMCR1:
+	case SPRN_MMCR2:
 		*spr_val = 0;
 		break;
 	default:
-- 
1.8.1.4

[PATCH 2/6] KVM: PPC: Book3S PR: Emulate TIR register

[Alexander Graf]

In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
Thread ID Register (TID). Since PR KVM doesn't emulate more than one thread
per core, we can just always expose 0 here.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 arch/powerpc/kvm/book3s_emulate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 914beb2..e4e54fb 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -563,6 +563,7 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
 	case SPRN_MMCR0:
 	case SPRN_MMCR1:
 	case SPRN_MMCR2:
+	case SPRN_TIR:
 		*spr_val = 0;
 		break;
 	default:
-- 
1.8.1.4

[PATCH 3/6] KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR

[Alexander Graf]

POWER8 introduced a new interrupt type called "Facility unavailable interrupt"
which contains its status message in a new register called FSCR.

Handle these exits and try to emulate instructions for unhandled facilities.
Follow-on patches enable KVM to expose specific facilities into the guest.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 arch/powerpc/include/asm/kvm_asm.h        | 18 +++++----
 arch/powerpc/include/asm/kvm_book3s_asm.h |  2 +
 arch/powerpc/include/asm/kvm_host.h       |  1 +
 arch/powerpc/kernel/asm-offsets.c         |  3 ++
 arch/powerpc/kvm/book3s.c                 | 10 +++++
 arch/powerpc/kvm/book3s_emulate.c         |  6 +++
 arch/powerpc/kvm/book3s_hv.c              |  6 ---
 arch/powerpc/kvm/book3s_pr.c              | 63 +++++++++++++++++++++++++++++++
 arch/powerpc/kvm/book3s_segment.S         | 25 ++++++++++++
 9 files changed, 120 insertions(+), 14 deletions(-)

diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index 19eb74a..9601741 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -102,6 +102,7 @@
 #define BOOK3S_INTERRUPT_PERFMON	0xf00
 #define BOOK3S_INTERRUPT_ALTIVEC	0xf20
 #define BOOK3S_INTERRUPT_VSX		0xf40
+#define BOOK3S_INTERRUPT_FAC_UNAVAIL	0xf60
 #define BOOK3S_INTERRUPT_H_FAC_UNAVAIL	0xf80
 
 #define BOOK3S_IRQPRIO_SYSTEM_RESET		0
@@ -114,14 +115,15 @@
 #define BOOK3S_IRQPRIO_FP_UNAVAIL		7
 #define BOOK3S_IRQPRIO_ALTIVEC			8
 #define BOOK3S_IRQPRIO_VSX			9
-#define BOOK3S_IRQPRIO_SYSCALL			10
-#define BOOK3S_IRQPRIO_MACHINE_CHECK		11
-#define BOOK3S_IRQPRIO_DEBUG			12
-#define BOOK3S_IRQPRIO_EXTERNAL			13
-#define BOOK3S_IRQPRIO_DECREMENTER		14
-#define BOOK3S_IRQPRIO_PERFORMANCE_MONITOR	15
-#define BOOK3S_IRQPRIO_EXTERNAL_LEVEL		16
-#define BOOK3S_IRQPRIO_MAX			17
+#define BOOK3S_IRQPRIO_FAC_UNAVAIL		10
+#define BOOK3S_IRQPRIO_SYSCALL			11
+#define BOOK3S_IRQPRIO_MACHINE_CHECK		12
+#define BOOK3S_IRQPRIO_DEBUG			13
+#define BOOK3S_IRQPRIO_EXTERNAL			14
+#define BOOK3S_IRQPRIO_DECREMENTER		15
+#define BOOK3S_IRQPRIO_PERFORMANCE_MONITOR	16
+#define BOOK3S_IRQPRIO_EXTERNAL_LEVEL		17
+#define BOOK3S_IRQPRIO_MAX			18
 
 #define BOOK3S_HFLAG_DCBZ32			0x1
 #define BOOK3S_HFLAG_SLB			0x2
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index 821725c..5bdfb5d 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -104,6 +104,7 @@ struct kvmppc_host_state {
 #ifdef CONFIG_PPC_BOOK3S_64
 	u64 cfar;
 	u64 ppr;
+	u64 host_fscr;
 #endif
 };
 
@@ -133,6 +134,7 @@ struct kvmppc_book3s_shadow_vcpu {
 		u64     esid;
 		u64     vsid;
 	} slb[64];			/* guest SLB */
+	u64 shadow_fscr;
 #endif
 };
 
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index 3fffb2e..e773a0e 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -475,6 +475,7 @@ struct kvm_vcpu_arch {
 	ulong ppr;
 	ulong pspb;
 	ulong fscr;
+	ulong shadow_fscr;
 	ulong ebbhr;
 	ulong ebbrr;
 	ulong bescr;
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index bc33da8..777e1ab 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -535,6 +535,7 @@ int main(void)
 	DEFINE(VCPU_CFAR, offsetof(struct kvm_vcpu, arch.cfar));
 	DEFINE(VCPU_PPR, offsetof(struct kvm_vcpu, arch.ppr));
 	DEFINE(VCPU_FSCR, offsetof(struct kvm_vcpu, arch.fscr));
+	DEFINE(VCPU_SHADOW_FSCR, offsetof(struct kvm_vcpu, arch.shadow_fscr));
 	DEFINE(VCPU_PSPB, offsetof(struct kvm_vcpu, arch.pspb));
 	DEFINE(VCPU_EBBHR, offsetof(struct kvm_vcpu, arch.ebbhr));
 	DEFINE(VCPU_EBBRR, offsetof(struct kvm_vcpu, arch.ebbrr));
@@ -616,6 +617,7 @@ int main(void)
 #ifdef CONFIG_PPC64
 	SVCPU_FIELD(SVCPU_SLB, slb);
 	SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
+	SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
 #endif
 
 	HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
@@ -651,6 +653,7 @@ int main(void)
 #ifdef CONFIG_PPC_BOOK3S_64
 	HSTATE_FIELD(HSTATE_CFAR, cfar);
 	HSTATE_FIELD(HSTATE_PPR, ppr);
+	HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
 #endif /* CONFIG_PPC_BOOK3S_64 */
 
 #else /* CONFIG_PPC_BOOK3S */
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index 81abc5c..79cfa2d 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -145,6 +145,7 @@ static int kvmppc_book3s_vec2irqprio(unsigned int vec)
 	case 0xd00: prio = BOOK3S_IRQPRIO_DEBUG;		break;
 	case 0xf20: prio = BOOK3S_IRQPRIO_ALTIVEC;		break;
 	case 0xf40: prio = BOOK3S_IRQPRIO_VSX;			break;
+	case 0xf60: prio = BOOK3S_IRQPRIO_FAC_UNAVAIL;		break;
 	default:    prio = BOOK3S_IRQPRIO_MAX;			break;
 	}
 
@@ -275,6 +276,9 @@ int kvmppc_book3s_irqprio_deliver(struct kvm_vcpu *vcpu, unsigned int priority)
 	case BOOK3S_IRQPRIO_PERFORMANCE_MONITOR:
 		vec = BOOK3S_INTERRUPT_PERFMON;
 		break;
+	case BOOK3S_IRQPRIO_FAC_UNAVAIL:
+		vec = BOOK3S_INTERRUPT_FAC_UNAVAIL;
+		break;
 	default:
 		deliver = 0;
 		printk(KERN_ERR "KVM: Unknown interrupt: 0x%x\n", priority);
@@ -627,6 +631,9 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
 			val = get_reg_val(reg->id, kvmppc_xics_get_icp(vcpu));
 			break;
 #endif /* CONFIG_KVM_XICS */
+		case KVM_REG_PPC_FSCR:
+			val = get_reg_val(reg->id, vcpu->arch.fscr);
+			break;
 		default:
 			r = -EINVAL;
 			break;
@@ -716,6 +723,9 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
 						set_reg_val(reg->id, val));
 			break;
 #endif /* CONFIG_KVM_XICS */
+		case KVM_REG_PPC_FSCR:
+			vcpu->arch.fscr = set_reg_val(reg->id, val);
+			break;
 		default:
 			r = -EINVAL;
 			break;
diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index e4e54fb..2639a63 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -438,6 +438,9 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
 	case SPRN_GQR7:
 		to_book3s(vcpu)->gqr[sprn - SPRN_GQR0] = spr_val;
 		break;
+	case SPRN_FSCR:
+		vcpu->arch.fscr = spr_val;
+		break;
 	case SPRN_ICTC:
 	case SPRN_THRM1:
 	case SPRN_THRM2:
@@ -543,6 +546,9 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
 	case SPRN_GQR7:
 		*spr_val = to_book3s(vcpu)->gqr[sprn - SPRN_GQR0];
 		break;
+	case SPRN_FSCR:
+		*spr_val = vcpu->arch.fscr;
+		break;
 	case SPRN_THRM1:
 	case SPRN_THRM2:
 	case SPRN_THRM3:
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 030821a..0092e12 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -879,9 +879,6 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
 	case KVM_REG_PPC_IAMR:
 		*val = get_reg_val(id, vcpu->arch.iamr);
 		break;
-	case KVM_REG_PPC_FSCR:
-		*val = get_reg_val(id, vcpu->arch.fscr);
-		break;
 	case KVM_REG_PPC_PSPB:
 		*val = get_reg_val(id, vcpu->arch.pspb);
 		break;
@@ -1091,9 +1088,6 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
 	case KVM_REG_PPC_IAMR:
 		vcpu->arch.iamr = set_reg_val(id, *val);
 		break;
-	case KVM_REG_PPC_FSCR:
-		vcpu->arch.fscr = set_reg_val(id, *val);
-		break;
 	case KVM_REG_PPC_PSPB:
 		vcpu->arch.pspb = set_reg_val(id, *val);
 		break;
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 96dbb5f..ae421dd 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -53,6 +53,7 @@
 
 static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr,
 			     ulong msr);
+static void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac);
 
 /* Some compatibility defines */
 #ifdef CONFIG_PPC_BOOK3S_32
@@ -115,6 +116,9 @@ void kvmppc_copy_to_svcpu(struct kvmppc_book3s_shadow_vcpu *svcpu,
 	svcpu->ctr = vcpu->arch.ctr;
 	svcpu->lr  = vcpu->arch.lr;
 	svcpu->pc  = vcpu->arch.pc;
+#ifdef CONFIG_PPC_BOOK3S_64
+	svcpu->shadow_fscr = vcpu->arch.shadow_fscr;
+#endif
 	svcpu->in_use = true;
 }
 
@@ -158,6 +162,9 @@ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu,
 	vcpu->arch.fault_dar   = svcpu->fault_dar;
 	vcpu->arch.fault_dsisr = svcpu->fault_dsisr;
 	vcpu->arch.last_inst   = svcpu->last_inst;
+#ifdef CONFIG_PPC_BOOK3S_64
+	vcpu->arch.shadow_fscr = svcpu->shadow_fscr;
+#endif
 	svcpu->in_use = false;
 
 out:
@@ -610,6 +617,17 @@ void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr)
 	kvmppc_recalc_shadow_msr(vcpu);
 }
 
+/* Give up facility (TAR / EBB / DSCR) */
+static void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac)
+{
+#ifdef CONFIG_PPC_BOOK3S_64
+	if (!(vcpu->arch.shadow_fscr & (1ULL << fac))) {
+		/* Facility not available to the guest, ignore giveup request*/
+		return;
+	}
+#endif
+}
+
 static int kvmppc_read_inst(struct kvm_vcpu *vcpu)
 {
 	ulong srr0 = kvmppc_get_pc(vcpu);
@@ -708,6 +726,14 @@ static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr,
 	return RESUME_GUEST;
 }
 
+static void kvmppc_trigger_fac_interrupt(struct kvm_vcpu *vcpu, ulong fac)
+{
+	/* Inject the Interrupt Cause field and trigger a guest interrupt */
+	vcpu->arch.fscr &= ~(0xffULL << 56);
+	vcpu->arch.fscr |= (fac << 56);
+	kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_FAC_UNAVAIL);
+}
+
 /*
  * Kernel code using FP or VMX could have flushed guest state to
  * the thread_struct; if so, get it back now.
@@ -733,6 +759,39 @@ static void kvmppc_handle_lost_ext(struct kvm_vcpu *vcpu)
 	current->thread.regs->msr |= lost_ext;
 }
 
+#ifdef CONFIG_PPC_BOOK3S_64
+
+static void kvmppc_emulate_fac(struct kvm_vcpu *vcpu, ulong fac)
+{
+	enum emulation_result er;
+	er = kvmppc_emulate_instruction(vcpu->run, vcpu);
+	if ((er != EMULATE_DONE) && (er != EMULATE_AGAIN)) {
+		/* Couldn't emulate, trigger interrupt in guest */
+		kvmppc_trigger_fac_interrupt(vcpu, fac);
+	}
+}
+
+/* Enable facilities (TAR, EBB, DSCR) for the guest */
+static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac)
+{
+	BUG_ON(!cpu_has_feature(CPU_FTR_ARCH_207S));
+
+	if (!(vcpu->arch.fscr & (1ULL << fac))) {
+		/* Facility not enabled by the guest */
+		kvmppc_trigger_fac_interrupt(vcpu, fac);
+		return RESUME_GUEST;
+	}
+
+	switch (fac) {
+	default:
+		kvmppc_emulate_fac(vcpu, fac);
+		break;
+	}
+
+	return RESUME_GUEST;
+}
+#endif
+
 int kvmppc_handle_exit_pr(struct kvm_run *run, struct kvm_vcpu *vcpu,
 			  unsigned int exit_nr)
 {
@@ -1007,6 +1066,10 @@ program_interrupt:
 		}
 		r = RESUME_GUEST;
 		break;
+	case BOOK3S_INTERRUPT_FAC_UNAVAIL:
+		kvmppc_handle_fac(vcpu, vcpu->arch.shadow_fscr >> 56);
+		r = RESUME_GUEST;
+		break;
 	case BOOK3S_INTERRUPT_MACHINE_CHECK:
 	case BOOK3S_INTERRUPT_TRACE:
 		kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
diff --git a/arch/powerpc/kvm/book3s_segment.S b/arch/powerpc/kvm/book3s_segment.S
index 1e0cc2a..acee37c 100644
--- a/arch/powerpc/kvm/book3s_segment.S
+++ b/arch/powerpc/kvm/book3s_segment.S
@@ -90,6 +90,15 @@ kvmppc_handler_trampoline_enter:
 	LOAD_GUEST_SEGMENTS
 
 #ifdef CONFIG_PPC_BOOK3S_64
+BEGIN_FTR_SECTION
+	/* Save host FSCR */
+	mfspr	r8, SPRN_FSCR
+	std	r8, HSTATE_HOST_FSCR(r13)
+	/* Set FSCR during guest execution */
+	ld	r9, SVCPU_SHADOW_FSCR(r13)
+	mtspr	SPRN_FSCR, r9
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
+
 	/* Some guests may need to have dcbz set to 32 byte length.
 	 *
 	 * Usually we ensure that by patching the guest's instructions
@@ -255,6 +264,10 @@ BEGIN_FTR_SECTION
 	cmpwi	r12, BOOK3S_INTERRUPT_H_EMUL_ASSIST
 	beq-	ld_last_inst
 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
+BEGIN_FTR_SECTION
+	cmpwi	r12, BOOK3S_INTERRUPT_FAC_UNAVAIL
+	beq-	ld_last_inst
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 #endif
 
 	b	no_ld_last_inst
@@ -311,6 +324,18 @@ no_ld_last_inst:
 
 no_dcbz32_off:
 
+BEGIN_FTR_SECTION
+	/* Save guest FSCR on a FAC_UNAVAIL interrupt */
+	cmpwi	r12, BOOK3S_INTERRUPT_FAC_UNAVAIL
+	bne+	no_fscr_save
+	mfspr	r7, SPRN_FSCR
+	std	r7, SVCPU_SHADOW_FSCR(r13)
+no_fscr_save:
+	/* Restore host FSCR */
+	ld	r8, HSTATE_HOST_FSCR(r13)
+	mtspr	SPRN_FSCR, r8
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
+
 #endif /* CONFIG_PPC_BOOK3S_64 */
 
 	/*
-- 
1.8.1.4

[PATCH 4/6] KVM: PPC: Book3S PR: Expose TAR facility to guest

[Alexander Graf]

POWER8 implements a new register called TAR. This register has to be
enabled in FSCR and then from KVM's point of view is mere storage.

This patch enables the guest to use TAR.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 arch/powerpc/include/asm/kvm_host.h |  2 ++
 arch/powerpc/kvm/book3s.c           |  6 ++++++
 arch/powerpc/kvm/book3s_hv.c        |  6 ------
 arch/powerpc/kvm/book3s_pr.c        | 18 ++++++++++++++++++
 4 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index e773a0e..e6c18d0 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -449,7 +449,9 @@ struct kvm_vcpu_arch {
 	ulong pc;
 	ulong ctr;
 	ulong lr;
+#ifdef CONFIG_PPC_BOOK3S
 	ulong tar;
+#endif
 
 	ulong xer;
 	u32 cr;
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index 79cfa2d..4046a1a 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -634,6 +634,9 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
 		case KVM_REG_PPC_FSCR:
 			val = get_reg_val(reg->id, vcpu->arch.fscr);
 			break;
+		case KVM_REG_PPC_TAR:
+			val = get_reg_val(reg->id, vcpu->arch.tar);
+			break;
 		default:
 			r = -EINVAL;
 			break;
@@ -726,6 +729,9 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
 		case KVM_REG_PPC_FSCR:
 			vcpu->arch.fscr = set_reg_val(reg->id, val);
 			break;
+		case KVM_REG_PPC_TAR:
+			vcpu->arch.tar = set_reg_val(reg->id, val);
+			break;
 		default:
 			r = -EINVAL;
 			break;
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 0092e12..ee1d8ee 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -891,9 +891,6 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
 	case KVM_REG_PPC_BESCR:
 		*val = get_reg_val(id, vcpu->arch.bescr);
 		break;
-	case KVM_REG_PPC_TAR:
-		*val = get_reg_val(id, vcpu->arch.tar);
-		break;
 	case KVM_REG_PPC_DPDES:
 		*val = get_reg_val(id, vcpu->arch.vcore->dpdes);
 		break;
@@ -1100,9 +1097,6 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
 	case KVM_REG_PPC_BESCR:
 		vcpu->arch.bescr = set_reg_val(id, *val);
 		break;
-	case KVM_REG_PPC_TAR:
-		vcpu->arch.tar = set_reg_val(id, *val);
-		break;
 	case KVM_REG_PPC_DPDES:
 		vcpu->arch.vcore->dpdes = set_reg_val(id, *val);
 		break;
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index ae421dd..9e22e7b 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -90,6 +90,7 @@ static void kvmppc_core_vcpu_put_pr(struct kvm_vcpu *vcpu)
 #endif
 
 	kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX);
+	kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
 	vcpu->cpu = -1;
 }
 
@@ -625,6 +626,14 @@ static void kvmppc_giveup_fac(struct kvm_vcpu *vcpu, ulong fac)
 		/* Facility not available to the guest, ignore giveup request*/
 		return;
 	}
+
+	switch (fac) {
+	case FSCR_TAR_LG:
+		vcpu->arch.tar = mfspr(SPRN_TAR);
+		mtspr(SPRN_TAR, current->thread.tar);
+		vcpu->arch.shadow_fscr &= ~FSCR_TAR;
+		break;
+	}
 #endif
 }
 
@@ -783,6 +792,12 @@ static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac)
 	}
 
 	switch (fac) {
+	case FSCR_TAR_LG:
+		/* TAR switching isn't lazy in Linux yet */
+		current->thread.tar = mfspr(SPRN_TAR);
+		mtspr(SPRN_TAR, vcpu->arch.tar);
+		vcpu->arch.shadow_fscr |= FSCR_TAR;
+		break;
 	default:
 		kvmppc_emulate_fac(vcpu, fac);
 		break;
@@ -1365,6 +1380,9 @@ static int kvmppc_vcpu_run_pr(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
 	/* Make sure we save the guest FPU/Altivec/VSX state */
 	kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX);
 
+	/* Make sure we save the guest TAR/EBB/DSCR state */
+	kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
+
 out:
 	vcpu->mode = OUTSIDE_GUEST_MODE;
 	return ret;
-- 
1.8.1.4

[PATCH 5/6] KVM: PPC: Book3S PR: Expose EBB registers

[Alexander Graf]

POWER8 introduces a new facility called the "Event Based Branch" facility.
It contains of a few registers that indicate where a guest should branch to
when a defined event occurs and it's in PR mode.

We don't want to really enable EBB as it will create a big mess with !PR guest
mode while hardware is in PR and we don't really emulate the PMU anyway.

So instead, let's just leave it at emulation of all its registers.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 arch/powerpc/kvm/book3s.c         | 18 ++++++++++++++++++
 arch/powerpc/kvm/book3s_emulate.c | 18 ++++++++++++++++++
 arch/powerpc/kvm/book3s_hv.c      | 18 ------------------
 3 files changed, 36 insertions(+), 18 deletions(-)

diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index 4046a1a..52c654d 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -637,6 +637,15 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
 		case KVM_REG_PPC_TAR:
 			val = get_reg_val(reg->id, vcpu->arch.tar);
 			break;
+		case KVM_REG_PPC_EBBHR:
+			val = get_reg_val(reg->id, vcpu->arch.ebbhr);
+			break;
+		case KVM_REG_PPC_EBBRR:
+			val = get_reg_val(reg->id, vcpu->arch.ebbrr);
+			break;
+		case KVM_REG_PPC_BESCR:
+			val = get_reg_val(reg->id, vcpu->arch.bescr);
+			break;
 		default:
 			r = -EINVAL;
 			break;
@@ -732,6 +741,15 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
 		case KVM_REG_PPC_TAR:
 			vcpu->arch.tar = set_reg_val(reg->id, val);
 			break;
+		case KVM_REG_PPC_EBBHR:
+			vcpu->arch.ebbhr = set_reg_val(reg->id, val);
+			break;
+		case KVM_REG_PPC_EBBRR:
+			vcpu->arch.ebbrr = set_reg_val(reg->id, val);
+			break;
+		case KVM_REG_PPC_BESCR:
+			vcpu->arch.bescr = set_reg_val(reg->id, val);
+			break;
 		default:
 			r = -EINVAL;
 			break;
diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 2639a63..d1ad257 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -441,6 +441,15 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
 	case SPRN_FSCR:
 		vcpu->arch.fscr = spr_val;
 		break;
+	case SPRN_BESCR:
+		vcpu->arch.bescr = spr_val;
+		break;
+	case SPRN_EBBHR:
+		vcpu->arch.ebbhr = spr_val;
+		break;
+	case SPRN_EBBRR:
+		vcpu->arch.ebbrr = spr_val;
+		break;
 	case SPRN_ICTC:
 	case SPRN_THRM1:
 	case SPRN_THRM2:
@@ -549,6 +558,15 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
 	case SPRN_FSCR:
 		*spr_val = vcpu->arch.fscr;
 		break;
+	case SPRN_BESCR:
+		*spr_val = vcpu->arch.bescr;
+		break;
+	case SPRN_EBBHR:
+		*spr_val = vcpu->arch.ebbhr;
+		break;
+	case SPRN_EBBRR:
+		*spr_val = vcpu->arch.ebbrr;
+		break;
 	case SPRN_THRM1:
 	case SPRN_THRM2:
 	case SPRN_THRM3:
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index ee1d8ee..3a94561 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -882,15 +882,6 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
 	case KVM_REG_PPC_PSPB:
 		*val = get_reg_val(id, vcpu->arch.pspb);
 		break;
-	case KVM_REG_PPC_EBBHR:
-		*val = get_reg_val(id, vcpu->arch.ebbhr);
-		break;
-	case KVM_REG_PPC_EBBRR:
-		*val = get_reg_val(id, vcpu->arch.ebbrr);
-		break;
-	case KVM_REG_PPC_BESCR:
-		*val = get_reg_val(id, vcpu->arch.bescr);
-		break;
 	case KVM_REG_PPC_DPDES:
 		*val = get_reg_val(id, vcpu->arch.vcore->dpdes);
 		break;
@@ -1088,15 +1079,6 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
 	case KVM_REG_PPC_PSPB:
 		vcpu->arch.pspb = set_reg_val(id, *val);
 		break;
-	case KVM_REG_PPC_EBBHR:
-		vcpu->arch.ebbhr = set_reg_val(id, *val);
-		break;
-	case KVM_REG_PPC_EBBRR:
-		vcpu->arch.ebbrr = set_reg_val(id, *val);
-		break;
-	case KVM_REG_PPC_BESCR:
-		vcpu->arch.bescr = set_reg_val(id, *val);
-		break;
 	case KVM_REG_PPC_DPDES:
 		vcpu->arch.vcore->dpdes = set_reg_val(id, *val);
 		break;
-- 
1.8.1.4

[PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers

[Alexander Graf]

POWER8 introduces transactional memory which brings along a number of new
registers and MSR bits.

Implementing all of those is a pretty big headache, so for now let's at least
emulate enough to make Linux's context switching code happy.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 arch/powerpc/kvm/book3s_emulate.c | 18 ++++++++++++++++++
 arch/powerpc/kvm/book3s_pr.c      |  3 ++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index d1ad257..870d9b8 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -450,6 +450,15 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
 	case SPRN_EBBRR:
 		vcpu->arch.ebbrr = spr_val;
 		break;
+	case SPRN_TFHAR:
+		vcpu->arch.tfhar = spr_val;
+		break;
+	case SPRN_TEXASR:
+		vcpu->arch.texasr = spr_val;
+		break;
+	case SPRN_TFIAR:
+		vcpu->arch.tfiar = spr_val;
+		break;
 	case SPRN_ICTC:
 	case SPRN_THRM1:
 	case SPRN_THRM2:
@@ -567,6 +576,15 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
 	case SPRN_EBBRR:
 		*spr_val = vcpu->arch.ebbrr;
 		break;
+	case SPRN_TFHAR:
+		*spr_val = vcpu->arch.tfhar;
+		break;
+	case SPRN_TEXASR:
+		*spr_val = vcpu->arch.texasr;
+		break;
+	case SPRN_TFIAR:
+		*spr_val = vcpu->arch.tfiar;
+		break;
 	case SPRN_THRM1:
 	case SPRN_THRM2:
 	case SPRN_THRM3:
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 9e22e7b..aeb87f6 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -785,7 +785,8 @@ static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac)
 {
 	BUG_ON(!cpu_has_feature(CPU_FTR_ARCH_207S));
 
-	if (!(vcpu->arch.fscr & (1ULL << fac))) {
+	/* We get TM interrupts only when EBB is disabled? Sigh. */
+	if ((fac != FSCR_TM_LG) && !(vcpu->arch.fscr & (1ULL << fac))) {
 		/* Facility not enabled by the guest */
 		kvmppc_trigger_fac_interrupt(vcpu, fac);
 		return RESUME_GUEST;
-- 
1.8.1.4

Re: [PATCH 2/6] KVM: PPC: Book3S PR: Emulate TIR register

[Michael Neuling]

> In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
> Thread ID Register (TID). Since PR KVM doesn't emulate more than one thread

s/TID/TIR/ above

> per core, we can just always expose 0 here.

I'm not sure if we ever do, but if we IPI ourselves using a doorbell,
we'll need to emulate the doorbell as well.

Mikey

> Signed-off-by: Alexander Graf <agraf@suse.de>
> ---
>  arch/powerpc/kvm/book3s_emulate.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
> index 914beb2..e4e54fb 100644
> --- a/arch/powerpc/kvm/book3s_emulate.c
> +++ b/arch/powerpc/kvm/book3s_emulate.c
> @@ -563,6 +563,7 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
>  	case SPRN_MMCR0:
>  	case SPRN_MMCR1:
>  	case SPRN_MMCR2:
> +	case SPRN_TIR:
>  		*spr_val = 0;
>  		break;
>  	default:
> -- 
> 1.8.1.4
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH 2/6] KVM: PPC: Book3S PR: Emulate TIR register

[Alexander Graf]

On 30.04.14 07:51, Michael Neuling wrote:
>> In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
>> Thread ID Register (TID). Since PR KVM doesn't emulate more than one thread
> s/TID/TIR/ above

Oops :)

>
>> per core, we can just always expose 0 here.
> I'm not sure if we ever do, but if we IPI ourselves using a doorbell,
> we'll need to emulate the doorbell as well.

Yeah, we don't. I'm surprised we don't myself, but I'd rather not 
implement the logic to emulate doorbells until I can easily verify it 
works - which means either have a Linux guest that does doorbells or 
have a test harness for kernel level test cases.


Alex

Re: [PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs

[Paul Mackerras]

On Tue, Apr 29, 2014 at 06:17:37PM +0200, Alexander Graf wrote:
> When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs
> that we don't emulate. Just ignore accesses to them.
> 
> Signed-off-by: Alexander Graf <agraf@suse.de>

This patch is OK as it stands, but in fact the architecture says that
kernel accesses to unimplemented SPRs are mostly supposed to be no-ops
rather than causing a trap (mostly == excluding mtspr to 0 or mfspr
from 0, 4, 5 or 6).  I have a patch to implement that, which I'll
post.

Paul.

Re: [PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs

[Alexander Graf]

On 05/01/2014 12:12 AM, Paul Mackerras wrote:
> On Tue, Apr 29, 2014 at 06:17:37PM +0200, Alexander Graf wrote:
>> When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs
>> that we don't emulate. Just ignore accesses to them.
>>
>> Signed-off-by: Alexander Graf <agraf@suse.de>
> This patch is OK as it stands, but in fact the architecture says that
> kernel accesses to unimplemented SPRs are mostly supposed to be no-ops
> rather than causing a trap (mostly == excluding mtspr to 0 or mfspr
> from 0, 4, 5 or 6).  I have a patch to implement that, which I'll
> post.

I think what we want is a flag similar to x86 where we can force ignore 
unknown SPRs, but leave it at triggering an interrupt as default. We 
usually have to be at least aware of unknown SPRs and check that not 
implementing them is ok for the guest.

Debugging a program interrupt because of an unknown SPR is usually a lot 
easier than debugging a breaking guest because it was using the SPR as 
storage and we didn't back it by anything.


Alex

Re: [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support

[Aneesh Kumar K.V]

Alexander Graf <agraf@suse.de> writes:

> When running on a POWER8 host, we get away with running the guest as POWER7
> and nothing falls apart.
>
> However, when we start exposing POWER8 as guest CPU, guests will start using
> new abilities on POWER8 which we need to handle.
>
> This patch set does a minimalistic approach to implementing those bits to
> make guests happy enough to run.
>
>
> Alex
>
> Alexander Graf (6):
>   KVM: PPC: Book3S PR: Ignore PMU SPRs
>   KVM: PPC: Book3S PR: Emulate TIR register
>   KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR
>   KVM: PPC: Book3S PR: Expose TAR facility to guest
>   KVM: PPC: Book3S PR: Expose EBB registers
>   KVM: PPC: Book3S PR: Expose TM registers
>
>  arch/powerpc/include/asm/kvm_asm.h        | 18 ++++---
>  arch/powerpc/include/asm/kvm_book3s_asm.h |  2 +
>  arch/powerpc/include/asm/kvm_host.h       |  3 ++
>  arch/powerpc/kernel/asm-offsets.c         |  3 ++
>  arch/powerpc/kvm/book3s.c                 | 34 +++++++++++++
>  arch/powerpc/kvm/book3s_emulate.c         | 53 ++++++++++++++++++++
>  arch/powerpc/kvm/book3s_hv.c              | 30 -----------
>  arch/powerpc/kvm/book3s_pr.c              | 82 +++++++++++++++++++++++++++++++
>  arch/powerpc/kvm/book3s_segment.S         | 25 ++++++++++
>  9 files changed, 212 insertions(+), 38 deletions(-)
>

I did most of this as part of 

[RFC PATCH 01/10] KVM: PPC: BOOK3S: PR: Add POWER8 support
http://mid.gmane.org/1390927455-3312-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com

Any reason why that is not picked up ? TM was the reason I didn't push the
patchset again. I was not sure how to get all the TM details to
work.

-aneesh

Re: [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support

[Alexander Graf]

On 05/04/2014 06:36 PM, Aneesh Kumar K.V wrote:
> Alexander Graf <agraf@suse.de> writes:
>
>> When running on a POWER8 host, we get away with running the guest as POWER7
>> and nothing falls apart.
>>
>> However, when we start exposing POWER8 as guest CPU, guests will start using
>> new abilities on POWER8 which we need to handle.
>>
>> This patch set does a minimalistic approach to implementing those bits to
>> make guests happy enough to run.
>>
>>
>> Alex
>>
>> Alexander Graf (6):
>>    KVM: PPC: Book3S PR: Ignore PMU SPRs
>>    KVM: PPC: Book3S PR: Emulate TIR register
>>    KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR
>>    KVM: PPC: Book3S PR: Expose TAR facility to guest
>>    KVM: PPC: Book3S PR: Expose EBB registers
>>    KVM: PPC: Book3S PR: Expose TM registers
>>
>>   arch/powerpc/include/asm/kvm_asm.h        | 18 ++++---
>>   arch/powerpc/include/asm/kvm_book3s_asm.h |  2 +
>>   arch/powerpc/include/asm/kvm_host.h       |  3 ++
>>   arch/powerpc/kernel/asm-offsets.c         |  3 ++
>>   arch/powerpc/kvm/book3s.c                 | 34 +++++++++++++
>>   arch/powerpc/kvm/book3s_emulate.c         | 53 ++++++++++++++++++++
>>   arch/powerpc/kvm/book3s_hv.c              | 30 -----------
>>   arch/powerpc/kvm/book3s_pr.c              | 82 +++++++++++++++++++++++++++++++
>>   arch/powerpc/kvm/book3s_segment.S         | 25 ++++++++++
>>   9 files changed, 212 insertions(+), 38 deletions(-)
>>
> I did most of this as part of
>
> [RFC PATCH 01/10] KVM: PPC: BOOK3S: PR: Add POWER8 support
> http://mid.gmane.org/1390927455-3312-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com
>
> Any reason why that is not picked up ? TM was the reason I didn't push the
> patchset again. I was not sure how to get all the TM details to
> work.

Ugh, I guess I mostly discarded it as brainstorm patches because they 
were marked RFC :(


Alex

Re: [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support

[Aneesh Kumar K.V]

Alexander Graf <agraf@suse.de> writes:

> On 05/04/2014 06:36 PM, Aneesh Kumar K.V wrote:
>> Alexander Graf <agraf@suse.de> writes:
>>
>>> When running on a POWER8 host, we get away with running the guest as POWER7
>>> and nothing falls apart.
>>>
>>> However, when we start exposing POWER8 as guest CPU, guests will start using
>>> new abilities on POWER8 which we need to handle.
>>>
>>> This patch set does a minimalistic approach to implementing those bits to
>>> make guests happy enough to run.
>>>
>>>
>>> Alex
>>>
>>> Alexander Graf (6):
>>>    KVM: PPC: Book3S PR: Ignore PMU SPRs
>>>    KVM: PPC: Book3S PR: Emulate TIR register
>>>    KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR
>>>    KVM: PPC: Book3S PR: Expose TAR facility to guest
>>>    KVM: PPC: Book3S PR: Expose EBB registers
>>>    KVM: PPC: Book3S PR: Expose TM registers
>>>
>>>   arch/powerpc/include/asm/kvm_asm.h        | 18 ++++---
>>>   arch/powerpc/include/asm/kvm_book3s_asm.h |  2 +
>>>   arch/powerpc/include/asm/kvm_host.h       |  3 ++
>>>   arch/powerpc/kernel/asm-offsets.c         |  3 ++
>>>   arch/powerpc/kvm/book3s.c                 | 34 +++++++++++++
>>>   arch/powerpc/kvm/book3s_emulate.c         | 53 ++++++++++++++++++++
>>>   arch/powerpc/kvm/book3s_hv.c              | 30 -----------
>>>   arch/powerpc/kvm/book3s_pr.c              | 82 +++++++++++++++++++++++++++++++
>>>   arch/powerpc/kvm/book3s_segment.S         | 25 ++++++++++
>>>   9 files changed, 212 insertions(+), 38 deletions(-)
>>>
>> I did most of this as part of
>>
>> [RFC PATCH 01/10] KVM: PPC: BOOK3S: PR: Add POWER8 support
>> http://mid.gmane.org/1390927455-3312-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com
>>
>> Any reason why that is not picked up ? TM was the reason I didn't push the
>> patchset again. I was not sure how to get all the TM details to
>> work.
>
> Ugh, I guess I mostly discarded it as brainstorm patches because they 
> were marked RFC :(
>

Do you want me to rework them ?. I guess facility unavailable part and
TM part in this series are better than what I had. Rest all are more or
less similar. Or you could cherry pick the SPR handling you haven't
added yet from this series ?

-aneesh

Re: [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support

[Alexander Graf]

On 05/05/2014 04:38 PM, Aneesh Kumar K.V wrote:
> Alexander Graf <agraf@suse.de> writes:
>
>> On 05/04/2014 06:36 PM, Aneesh Kumar K.V wrote:
>>> Alexander Graf <agraf@suse.de> writes:
>>>
>>>> When running on a POWER8 host, we get away with running the guest as POWER7
>>>> and nothing falls apart.
>>>>
>>>> However, when we start exposing POWER8 as guest CPU, guests will start using
>>>> new abilities on POWER8 which we need to handle.
>>>>
>>>> This patch set does a minimalistic approach to implementing those bits to
>>>> make guests happy enough to run.
>>>>
>>>>
>>>> Alex
>>>>
>>>> Alexander Graf (6):
>>>>     KVM: PPC: Book3S PR: Ignore PMU SPRs
>>>>     KVM: PPC: Book3S PR: Emulate TIR register
>>>>     KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR
>>>>     KVM: PPC: Book3S PR: Expose TAR facility to guest
>>>>     KVM: PPC: Book3S PR: Expose EBB registers
>>>>     KVM: PPC: Book3S PR: Expose TM registers
>>>>
>>>>    arch/powerpc/include/asm/kvm_asm.h        | 18 ++++---
>>>>    arch/powerpc/include/asm/kvm_book3s_asm.h |  2 +
>>>>    arch/powerpc/include/asm/kvm_host.h       |  3 ++
>>>>    arch/powerpc/kernel/asm-offsets.c         |  3 ++
>>>>    arch/powerpc/kvm/book3s.c                 | 34 +++++++++++++
>>>>    arch/powerpc/kvm/book3s_emulate.c         | 53 ++++++++++++++++++++
>>>>    arch/powerpc/kvm/book3s_hv.c              | 30 -----------
>>>>    arch/powerpc/kvm/book3s_pr.c              | 82 +++++++++++++++++++++++++++++++
>>>>    arch/powerpc/kvm/book3s_segment.S         | 25 ++++++++++
>>>>    9 files changed, 212 insertions(+), 38 deletions(-)
>>>>
>>> I did most of this as part of
>>>
>>> [RFC PATCH 01/10] KVM: PPC: BOOK3S: PR: Add POWER8 support
>>> http://mid.gmane.org/1390927455-3312-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com
>>>
>>> Any reason why that is not picked up ? TM was the reason I didn't push the
>>> patchset again. I was not sure how to get all the TM details to
>>> work.
>> Ugh, I guess I mostly discarded it as brainstorm patches because they
>> were marked RFC :(
>>
> Do you want me to rework them ?. I guess facility unavailable part and
> TM part in this series are better than what I had. Rest all are more or
> less similar. Or you could cherry pick the SPR handling you haven't
> added yet from this series ?

I personally refuse to apply patches that are marked RFC, since IMHO on 
those the author himself isn't sure he wants them applied yet :).

I'd say I'll just apply mine after another autotest run and then you 
rebase your things on top and fill the gaps with a real, non-RFC patch set.


Alex

Re: [PATCH 0/6] KVM: PPC: Book3S PR: Add POWER8 support

[Aneesh Kumar K.V]

Alexander Graf <agraf@suse.de> writes:

> On 05/05/2014 04:38 PM, Aneesh Kumar K.V wrote:
>> Alexander Graf <agraf@suse.de> writes:
>>
>>> On 05/04/2014 06:36 PM, Aneesh Kumar K.V wrote:
>>>> Alexander Graf <agraf@suse.de> writes:
>>>>
>>>>> When running on a POWER8 host, we get away with running the guest as POWER7
>>>>> and nothing falls apart.
>>>>>
>>>>> However, when we start exposing POWER8 as guest CPU, guests will start using
>>>>> new abilities on POWER8 which we need to handle.
>>>>>
>>>>> This patch set does a minimalistic approach to implementing those bits to
>>>>> make guests happy enough to run.
>>>>>
>>>>>
>>>>> Alex
>>>>>
>>>>> Alexander Graf (6):
>>>>>     KVM: PPC: Book3S PR: Ignore PMU SPRs
>>>>>     KVM: PPC: Book3S PR: Emulate TIR register
>>>>>     KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR
>>>>>     KVM: PPC: Book3S PR: Expose TAR facility to guest
>>>>>     KVM: PPC: Book3S PR: Expose EBB registers
>>>>>     KVM: PPC: Book3S PR: Expose TM registers
>>>>>
>>>>>    arch/powerpc/include/asm/kvm_asm.h        | 18 ++++---
>>>>>    arch/powerpc/include/asm/kvm_book3s_asm.h |  2 +
>>>>>    arch/powerpc/include/asm/kvm_host.h       |  3 ++
>>>>>    arch/powerpc/kernel/asm-offsets.c         |  3 ++
>>>>>    arch/powerpc/kvm/book3s.c                 | 34 +++++++++++++
>>>>>    arch/powerpc/kvm/book3s_emulate.c         | 53 ++++++++++++++++++++
>>>>>    arch/powerpc/kvm/book3s_hv.c              | 30 -----------
>>>>>    arch/powerpc/kvm/book3s_pr.c              | 82 +++++++++++++++++++++++++++++++
>>>>>    arch/powerpc/kvm/book3s_segment.S         | 25 ++++++++++
>>>>>    9 files changed, 212 insertions(+), 38 deletions(-)
>>>>>
>>>> I did most of this as part of
>>>>
>>>> [RFC PATCH 01/10] KVM: PPC: BOOK3S: PR: Add POWER8 support
>>>> http://mid.gmane.org/1390927455-3312-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com
>>>>
>>>> Any reason why that is not picked up ? TM was the reason I didn't push the
>>>> patchset again. I was not sure how to get all the TM details to
>>>> work.
>>> Ugh, I guess I mostly discarded it as brainstorm patches because they
>>> were marked RFC :(
>>>
>> Do you want me to rework them ?. I guess facility unavailable part and
>> TM part in this series are better than what I had. Rest all are more or
>> less similar. Or you could cherry pick the SPR handling you haven't
>> added yet from this series ?
>
> I personally refuse to apply patches that are marked RFC, since IMHO on 
> those the author himself isn't sure he wants them applied yet :).
>
> I'd say I'll just apply mine after another autotest run and then you 
> rebase your things on top and fill the gaps with a real, non-RFC patch set.

Will do

-aneesh

Re: [PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs

[Paul Mackerras]

On Fri, May 02, 2014 at 10:35:09AM +0200, Alexander Graf wrote:
> On 05/01/2014 12:12 AM, Paul Mackerras wrote:
> >On Tue, Apr 29, 2014 at 06:17:37PM +0200, Alexander Graf wrote:
> >>When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs
> >>that we don't emulate. Just ignore accesses to them.
> >>
> >>Signed-off-by: Alexander Graf <agraf@suse.de>
> >This patch is OK as it stands, but in fact the architecture says that
> >kernel accesses to unimplemented SPRs are mostly supposed to be no-ops
> >rather than causing a trap (mostly == excluding mtspr to 0 or mfspr
> >from 0, 4, 5 or 6).  I have a patch to implement that, which I'll
> >post.
> 
> I think what we want is a flag similar to x86 where we can force
> ignore unknown SPRs, but leave it at triggering an interrupt as
> default. We usually have to be at least aware of unknown SPRs and
> check that not implementing them is ok for the guest.
> 
> Debugging a program interrupt because of an unknown SPR is usually a
> lot easier than debugging a breaking guest because it was using the
> SPR as storage and we didn't back it by anything.

That has not been my experience, for accesses by the Linux kernel
early in the boot process; usually we end up in a loop of ISI
interrupts because the HPT isn't set up yet, with the original
interrupt cause (and PC) lost long ago.

The Power ISA was changed in version 2.05 (POWER6) to specify that
accesses to unimplemented SPRs by privileged code must be no-ops on
server processors.  Before that the architecture allowed either an
illegal instruction interrupt or "boundedly undefined" behaviour
(which would include a no-op).

So, if we're emulating POWERx for x >= 6, to be correct we need to do
the no-op behaviour, even if we retain the option of making them trap
for debugging purposes.  Of course at the moment we basically never
look at what specific CPU we're emulating, but maybe now we have to.

Regards,
Paul.

Re: [PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs

[Alexander Graf]

On 05/07/2014 09:09 AM, Paul Mackerras wrote:
> On Fri, May 02, 2014 at 10:35:09AM +0200, Alexander Graf wrote:
>> On 05/01/2014 12:12 AM, Paul Mackerras wrote:
>>> On Tue, Apr 29, 2014 at 06:17:37PM +0200, Alexander Graf wrote:
>>>> When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs
>>>> that we don't emulate. Just ignore accesses to them.
>>>>
>>>> Signed-off-by: Alexander Graf <agraf@suse.de>
>>> This patch is OK as it stands, but in fact the architecture says that
>>> kernel accesses to unimplemented SPRs are mostly supposed to be no-ops
>>> rather than causing a trap (mostly == excluding mtspr to 0 or mfspr
>> >from 0, 4, 5 or 6).  I have a patch to implement that, which I'll
>>> post.
>> I think what we want is a flag similar to x86 where we can force
>> ignore unknown SPRs, but leave it at triggering an interrupt as
>> default. We usually have to be at least aware of unknown SPRs and
>> check that not implementing them is ok for the guest.
>>
>> Debugging a program interrupt because of an unknown SPR is usually a
>> lot easier than debugging a breaking guest because it was using the
>> SPR as storage and we didn't back it by anything.
> That has not been my experience, for accesses by the Linux kernel
> early in the boot process; usually we end up in a loop of ISI
> interrupts because the HPT isn't set up yet, with the original
> interrupt cause (and PC) lost long ago.
>
> The Power ISA was changed in version 2.05 (POWER6) to specify that
> accesses to unimplemented SPRs by privileged code must be no-ops on
> server processors.  Before that the architecture allowed either an
> illegal instruction interrupt or "boundedly undefined" behaviour
> (which would include a no-op).
>
> So, if we're emulating POWERx for x >= 6, to be correct we need to do
> the no-op behaviour, even if we retain the option of making them trap
> for debugging purposes.  Of course at the moment we basically never
> look at what specific CPU we're emulating, but maybe now we have to.

I think it makes sense to have some more detailed knowledge of the 
target CPU we're modeling for other reasons, but for this we should just 
settle on either trapping or not trapping by default.

Finding the root cause of an ISI storm is easy when you run traces. 
Finding the root cause of a null pointer exception because Linux was 
trying to read from somewhere it mfspr()'d before requires quite a bit 
more knowledge of what's going on.


Alex

Re: [PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers

[Paul Mackerras]

On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
> POWER8 introduces transactional memory which brings along a number of new
> registers and MSR bits.
> 
> Implementing all of those is a pretty big headache, so for now let's at least
> emulate enough to make Linux's context switching code happy.

[snip]

> -	if (!(vcpu->arch.fscr & (1ULL << fac))) {
> +	/* We get TM interrupts only when EBB is disabled? Sigh. */

This comment doesn't make sense to me.  Not every reason code reported
in the high bits of FSCR corresponds directly to an enable bit in
FSCR.  In fact, of the 7 defined reason codes in POWER8, only three
correspond to an enable bit...

> +	if ((fac != FSCR_TM_LG) && !(vcpu->arch.fscr & (1ULL << fac))) {

so this should really check explicitly for TAR, EBB or DSCR.

Paul.

Re: [PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers

[Alexander Graf]

On 17.05.14 08:20, Paul Mackerras wrote:
> On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
>> POWER8 introduces transactional memory which brings along a number of new
>> registers and MSR bits.
>>
>> Implementing all of those is a pretty big headache, so for now let's at least
>> emulate enough to make Linux's context switching code happy.
> [snip]
>
>> -	if (!(vcpu->arch.fscr & (1ULL << fac))) {
>> +	/* We get TM interrupts only when EBB is disabled? Sigh. */
> This comment doesn't make sense to me.  Not every reason code reported
> in the high bits of FSCR corresponds directly to an enable bit in
> FSCR.  In fact, of the 7 defined reason codes in POWER8, only three
> correspond to an enable bit...

Is there any documentation on which relate to what?


Alex

>
>> +	if ((fac != FSCR_TM_LG) && !(vcpu->arch.fscr & (1ULL << fac))) {
> so this should really check explicitly for TAR, EBB or DSCR.
>
> Paul.
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Re: [PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers

[Paul Mackerras]

On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
> 
> On 17.05.14 08:20, Paul Mackerras wrote:
> >On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
> >>POWER8 introduces transactional memory which brings along a number of new
> >>registers and MSR bits.
> >>
> >>Implementing all of those is a pretty big headache, so for now let's at least
> >>emulate enough to make Linux's context switching code happy.
> >[snip]
> >
> >>-	if (!(vcpu->arch.fscr & (1ULL << fac))) {
> >>+	/* We get TM interrupts only when EBB is disabled? Sigh. */
> >This comment doesn't make sense to me.  Not every reason code reported
> >in the high bits of FSCR corresponds directly to an enable bit in
> >FSCR.  In fact, of the 7 defined reason codes in POWER8, only three
> >correspond to an enable bit...
> 
> Is there any documentation on which relate to what?

Yes, Power ISA v2.07 book 3S section 6.2.10 describes the FSCR enable
bits and the interruption cause field.  There are 6 cause values
defined, of which 3 correspond to enable bits in the FSCR, and the
other 3 correspond to things enabled/disabled in MMCR0 (usermode PMC
anb BHRB access) or MSR (TM stuff).

Paul.

Re: [PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers

[Alexander Graf]

On 20.05.2014, at 11:59, Paul Mackerras <paulus@samba.org> wrote:

> On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
>> 
>> On 17.05.14 08:20, Paul Mackerras wrote:
>>> On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
>>>> POWER8 introduces transactional memory which brings along a number of new
>>>> registers and MSR bits.
>>>> 
>>>> Implementing all of those is a pretty big headache, so for now let's at least
>>>> emulate enough to make Linux's context switching code happy.
>>> [snip]
>>> 
>>>> -	if (!(vcpu->arch.fscr & (1ULL << fac))) {
>>>> +	/* We get TM interrupts only when EBB is disabled? Sigh. */
>>> This comment doesn't make sense to me.  Not every reason code reported
>>> in the high bits of FSCR corresponds directly to an enable bit in
>>> FSCR.  In fact, of the 7 defined reason codes in POWER8, only three
>>> correspond to an enable bit...
>> 
>> Is there any documentation on which relate to what?
> 
> Yes, Power ISA v2.07 book 3S section 6.2.10 describes the FSCR enable
> bits and the interruption cause field.  There are 6 cause values
> defined, of which 3 correspond to enable bits in the FSCR, and the
> other 3 correspond to things enabled/disabled in MMCR0 (usermode PMC
> anb BHRB access) or MSR (TM stuff).

I see. How's this?

Alex

commit a8e53f5f5e6c5d99363ad0d695a9ee520e1d262d
Author: Alexander Graf <agraf@suse.de>
Date:   Tue Apr 29 17:54:40 2014 +0200

    KVM: PPC: Book3S PR: Expose TM registers

    POWER8 introduces transactional memory which brings along a number of new
    registers and MSR bits.

    Implementing all of those is a pretty big headache, so for now let's at least
    emulate enough to make Linux's context switching code happy.

    Signed-off-by: Alexander Graf <agraf@suse.de>

    ---

    v1 -> v2:

      - move to book3s_64 only section
      - restrict to CONFIG_PPC_TRANSACTIONAL_MEM

    v2 -> v3:

      - check MSR.TM for TM enablement inside the guest

diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index e1165ba..9bdff15 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -451,6 +451,17 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
 	case SPRN_EBBRR:
 		vcpu->arch.ebbrr = spr_val;
 		break;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	case SPRN_TFHAR:
+		vcpu->arch.tfhar = spr_val;
+		break;
+	case SPRN_TEXASR:
+		vcpu->arch.texasr = spr_val;
+		break;
+	case SPRN_TFIAR:
+		vcpu->arch.tfiar = spr_val;
+		break;
+#endif
 #endif
 	case SPRN_ICTC:
 	case SPRN_THRM1:
@@ -572,6 +583,17 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
 	case SPRN_EBBRR:
 		*spr_val = vcpu->arch.ebbrr;
 		break;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	case SPRN_TFHAR:
+		*spr_val = vcpu->arch.tfhar;
+		break;
+	case SPRN_TEXASR:
+		*spr_val = vcpu->arch.texasr;
+		break;
+	case SPRN_TFIAR:
+		*spr_val = vcpu->arch.tfiar;
+		break;
+#endif
 #endif
 	case SPRN_THRM1:
 	case SPRN_THRM2:
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 7d27a95..23367a7 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -794,9 +794,27 @@ static void kvmppc_emulate_fac(struct kvm_vcpu *vcpu, ulong fac)
 /* Enable facilities (TAR, EBB, DSCR) for the guest */
 static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac)
 {
+	bool guest_fac_enabled;
 	BUG_ON(!cpu_has_feature(CPU_FTR_ARCH_207S));

-	if (!(vcpu->arch.fscr & (1ULL << fac))) {
+	/*
+	 * Not every facility is enabled by FSCR bits, check whether the
+	 * guest has this facility enabled at all.
+	 */
+	switch (fac) {
+	case FSCR_TAR_LG:
+	case FSCR_EBB_LG:
+		guest_fac_enabled = (vcpu->arch.fscr & (1ULL << fac));
+		break;
+	case FSCR_TM_LG:
+		guest_fac_enabled = kvmppc_get_msr(vcpu) & MSR_TM;
+		break;
+	default:
+		guest_fac_enabled = false;
+		break;
+	}
+
+	if (!guest_fac_enabled) {
 		/* Facility not enabled by the guest */
 		kvmppc_trigger_fac_interrupt(vcpu, fac);
 		return RESUME_GUEST;