From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Subject: Re: [PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers Date: Mon, 19 May 2014 15:09:07 +0200 Message-ID: <537A0273.1070704@suse.de> References: <1398788262-3307-1-git-send-email-agraf@suse.de> <1398788262-3307-7-git-send-email-agraf@suse.de> <20140517062036.GC22449@iris.ozlabs.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org To: Paul Mackerras Return-path: Received: from cantor2.suse.de ([195.135.220.15]:59400 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753570AbaESNJK (ORCPT ); Mon, 19 May 2014 09:09:10 -0400 In-Reply-To: <20140517062036.GC22449@iris.ozlabs.ibm.com> Sender: kvm-owner@vger.kernel.org List-ID: On 17.05.14 08:20, Paul Mackerras wrote: > On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote: >> POWER8 introduces transactional memory which brings along a number of new >> registers and MSR bits. >> >> Implementing all of those is a pretty big headache, so for now let's at least >> emulate enough to make Linux's context switching code happy. > [snip] > >> - if (!(vcpu->arch.fscr & (1ULL << fac))) { >> + /* We get TM interrupts only when EBB is disabled? Sigh. */ > This comment doesn't make sense to me. Not every reason code reported > in the high bits of FSCR corresponds directly to an enable bit in > FSCR. In fact, of the 7 defined reason codes in POWER8, only three > correspond to an enable bit... Is there any documentation on which relate to what? Alex > >> + if ((fac != FSCR_TM_LG) && !(vcpu->arch.fscr & (1ULL << fac))) { > so this should really check explicitly for TAR, EBB or DSCR. > > Paul. > -- > To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html