From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Subject: Re: [PATCH 6/7] KVM: PPC: Book3S HV: Work around POWER8 performance monitor bugs Date: Sun, 25 May 2014 12:07:40 +0200 Message-ID: <5381C0EC.70208@suse.de> References: <1400919721-14264-1-git-send-email-paulus@samba.org> <1400919721-14264-7-git-send-email-paulus@samba.org> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org To: Paul Mackerras Return-path: Received: from cantor2.suse.de ([195.135.220.15]:54741 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751375AbaEYKHm (ORCPT ); Sun, 25 May 2014 06:07:42 -0400 In-Reply-To: <1400919721-14264-7-git-send-email-paulus@samba.org> Sender: kvm-owner@vger.kernel.org List-ID: On 24.05.14 10:22, Paul Mackerras wrote: > This adds workarounds for two hardware bugs in the POWER8 performance > monitor unit (PMU), both related to interrupt generation. The effect > of these bugs is that PMU interrupts can get lost, leading to tools > such as perf reporting fewer counts and samples than they should. > > The first bug relates to the PMAO (perf. mon. alert occurred) bit in > MMCR0; setting it should cause an interrupt, but doesn't. The other > bug relates to the PMAE (perf. mon. alert enable) bit in MMCR0. > Setting PMAE when a counter is negative and counter negative > conditions are enabled to cause alerts should cause an alert, but > doesn't. > > The workaround for the first bug is to create conditions where a > counter will overflow, whenever we are about to restore a MMCR0 > value that has PMAO set (and PMAO_SYNC clear). The workaround for > the second bug is to freeze all counters using MMCR2 before reading > MMCR0. > > Signed-off-by: Paul Mackerras I seriously hope you're actively working on converting this whole file to C code :). Alex