[PATCH 5/6] KVM: PPC: Book3S HV: Access XICS in BE

Alexander Graf
2014-06-11T10:33:54Z

On the exit path from the guest we check what type of interrupt we received
if we received one. This means we're doing hardware access to the XICS interrupt
controller.

However, when running on a little endian system, this access is byte reversed.

So let's make sure to swizzle the bytes back again and virtuall make XICS
accesses big endian.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 3530d06..40dec37 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -36,6 +36,13 @@
#define NAPPING_CEDE 1
#define NAPPING_NOVCPU 2

+.macro bswap32 regd, regs
+ srwi \regd,\regs,24
+ rlwimi \regd,\regs,24,16,23
+ rlwimi \regd,\regs,8,8,15
+ rlwimi \regd,\regs,24,0,7
+.endm
+
/*
* Call kvmppc_hv_entry in real mode.
* Must be called with interrupts hard-disabled.
@@ -2206,7 +2213,12 @@ kvmppc_read_intr:
cmpdi r6, 0
beq- 1f
lwzcix r0, r6, r7
- rlwinm. r3, r0, 0, 0xffffff
+#ifdef __LITTLE_ENDIAN__
+ bswap32 r3, r0
+#else
+ mr r3, r0
+#endif
+ rlwinm. r3, r3, 0, 0xffffff
sync
beq 1f /* if nothing pending in the ICP */

@@ -2241,7 +2253,8 @@ kvmppc_read_intr:
42: /* It's not an IPI and it's for the host, stash it in the PACA
* before exit, it will be picked up by the host ICP driver
*/
- stw r0, HSTATE_SAVED_XIRR(r13)
+ li r4, HSTATE_SAVED_XIRR
+ STWX_BE r0, r13, r4
li r3, 1
b 1b

--
1.8.1.4