Re: [PATCH 5/6] KVM: PPC: Book3S HV: Access XICS in BE

Paul Mackerras
2014-06-17T12:13:30Z

On Tue, Jun 17, 2014 at 12:22:32PM +0200, Alexander Graf wrote:
>
> Eh, no. What we do is we read (good on BE, byte reversed) into r0. Then we
> swab32() from r0 to r3 on LE, mr from r0 to r3 on BE.
>
> r3 gets truncated along the way.
>
> The reason we maintain r0 as wrong-endian is that we write it back using the
> cache inhibited stwcix instruction:
>
> > stwcix r0, r6, r7 /* EOI it */
>
> So during the lifetime of r0 as XIRR it's always byte-reversed on LE. That's
> why we store it using STWX_BE into hstate, because that's the time when we
> actually swab32() it for further interpretation.

So the STWX_BE is more like a be32_to_cpu than a cpu_to_be32, which is
what the name STWX_BE would suggest. Sounds like it at least deserves
a comment, or (as you suggest) rearrange the register usage so a
normal store works.

Paul.