From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH v2] KVM: x86: keep eoi exit bitmap accurate before loading it. Date: Thu, 28 Aug 2014 10:44:04 +0200 Message-ID: <53FEEBD4.8030202@redhat.com> References: <1409148331-5964-1-git-send-email-wei.w.wang@intel.com> <53FDEAC2.7020906@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Cc: "alex.williamson@redhat.com" To: "Zhang, Yang Z" , "Wang, Wei W" , "kvm@vger.kernel.org" Return-path: Received: from mail-wi0-f170.google.com ([209.85.212.170]:42087 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932445AbaH1IoL (ORCPT ); Thu, 28 Aug 2014 04:44:11 -0400 Received: by mail-wi0-f170.google.com with SMTP id cc10so172846wib.5 for ; Thu, 28 Aug 2014 01:44:10 -0700 (PDT) In-Reply-To: Sender: kvm-owner@vger.kernel.org List-ID: Il 28/08/2014 08:17, Zhang, Yang Z ha scritto: > > Program edge-triggered MSI for vector 123 > > Interrupt comes in, ISR[123]=1 > > Mask MSI > > Program level-triggered IOAPIC interrupt for vector 123 > > You cannot assign the vector 123 to another trigger mode interrupt > before previous IRQ handler finished (means issue EOI). If there is an > interrupt comes from the IOAPIC entry immediately after you reprogram > the entry, it will update the TMR to 1. Since we are still in previous > IRQ handler, it will get confused to see the TMR becomes 1. Yeah, that could be confusing to real hardware as well. Still, I'm a bit nervous at the possibility of races introduced by these patches... I wouldn't mind a second review. Paolo