From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH 0/3] kvm: APICv register write workaround Date: Fri, 31 Oct 2014 16:06:49 +0100 Message-ID: <5453A589.6040308@redhat.com> References: <1414678007-9377-1-git-send-email-rkrcmar@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: kvm@vger.kernel.org, Gleb Natapov , Marcelo Tosatti To: =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , linux-kernel@vger.kernel.org Return-path: In-Reply-To: <1414678007-9377-1-git-send-email-rkrcmar@redhat.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On 30/10/2014 15:06, Radim Kr=C4=8Dm=C3=A1=C5=99 wrote: > APICv traps register writes, so we can't retrieve previous value, but > our code depends on detecting changes. Applied, thanks. Paolo > Apart from disabling APIC register virtualization, we can detect the > change by using extra memory. One value history is enough, but we st= ill > don't want to keep it for every APIC register, for performance reason= s. > This leaves us with either a new framework, or exceptions ... > The latter options fits KVM's path better [1,2]. >=20 > And when we already mirror a part of registers, optimizing access is > acceptable [3]. (Squashed to keep bisecters happy.) >=20 > --- > Radim Kr=C4=8Dm=C3=A1=C5=99 (3): > KVM: x86: detect SPIV changes under APICv > KVM: x86: detect LVTT changes under APICv > KVM: x86: optimize some accesses to LVTT and SPIV >=20 > arch/x86/kvm/lapic.c | 32 +++++++++++++++++--------------- > arch/x86/kvm/lapic.h | 8 +++++--- > 2 files changed, 22 insertions(+), 18 deletions(-) >=20