Re: Seeking a KVM benchmark

Paolo Bonzini
2014-11-12T11:33:38Z

On 10/11/2014 18:38, Gleb Natapov wrote:
> On Mon, Nov 10, 2014 at 06:28:25PM +0100, Paolo Bonzini wrote:
>> On 10/11/2014 15:23, Avi Kivity wrote:
>>> It's not surprising [1]. Since the meaning of some PTE bits change [2],
>>> the TLB has to be flushed. In VMX we have VPIDs, so we only need to flush
>>> if EFER changed between two invocations of the same VPID, which isn't the
>>> case.
>>>
>>> [1] after the fact
>>> [2] although those bits were reserved with NXE=0, so they shouldn't have
>>> any TLB footprint
>>
>> You're right that this is not that surprising after the fact, and that
>> both Sandy Bridge and Ivy Bridge have VPIDs (even the non-Xeon ones).
>> This is also why I'm curious about the Nehalem.
>>
>> However note that even toggling the SCE bit is flushing the TLB. The
>> NXE bit is not being toggled here! That's the more surprising part.
>>
> Just a guess, but may be because writing EFER is not something that happens
> often in regular OSes it is not optimized to handle different bits differently.

Yes, that's what Intel said too.

Nehalem results:

userspace exit, urn 17560 17726 17628 17572 17417
lightweight exit, urn 3316 3342 3342 3319 3328
userspace exit, LOAD_EFER, guest!=host 12200 11772 12130 12164 12327
lightweight exit, LOAD_EFER, guest!=host 3214 3220 3238 3218 3337
userspace exit, LOAD_EFER, guest=host 11983 11780 11920 11919 12040
lightweight exit, LOAD_EFER, guest=host 3178 3193 3193 3187 3220

So the benchmark results also explain why skipping the LOAD_EFER does
not give a benefit for guest EFER=host EFER.

Paolo