Re: Seeking a KVM benchmark

[Wanpeng Li <kernellwp@gmail.com>]

Hi Paolo,
On 11/11/14, 1:28 AM, Paolo Bonzini wrote:
> On 10/11/2014 15:23, Avi Kivity wrote:
>> It's not surprising [1].  Since the meaning of some PTE bits change [2],
>> the TLB has to be flushed.  In VMX we have VPIDs, so we only need to flush
>> if EFER changed between two invocations of the same VPID, which isn't the
>> case.

If there need a TLB flush if guest is UP?

Regards,
Wanpeng Li

>>
>> [1] after the fact
>> [2] although those bits were reserved with NXE=0, so they shouldn't have
>> any TLB footprint
> You're right that this is not that surprising after the fact, and that
> both Sandy Bridge and Ivy Bridge have VPIDs (even the non-Xeon ones).
> This is also why I'm curious about the Nehalem.
>
> However note that even toggling the SCE bit is flushing the TLB.  The
> NXE bit is not being toggled here!  That's the more surprising part.
>
> Paolo
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