Re: [PATCH 3/3] arm, arm64: KVM: handle potential incoherency of readonly memslots

Paolo Bonzini
2014-11-17T16:03:16Z

On 17/11/2014 16:39, Marc Zyngier wrote:
> ARM is broadly similar, but there's a number of gotchas:
> - uncacheable (guest level) + cacheable (host level) -> uncacheable: the
> read request is going to be directly sent to RAM, bypassing the caches.
> - Userspace is going to use a cacheable view of the "NOR" pages, which
> is going to stick around in the cache (this is just memory, after all).

Ah, x86 also has uncacheable + cacheable -> uncacheable, but Intel also
added a bit to ignore the guest-provided type. We use that bit for
RAM-backed areas.

Also, on x86 if the cache is disabled the processor will still snoop
caches (including its own cache) and perform writeback+invalidate of the
cache line before accessing main memory, if it's dirty. AMD does not
have the aforementioned bit, but applies this same algorithm if the host
says the page is writeback in the MTRR (memory type range register).
The Intel solution is less tricky and has better performance.

Paolo

> The net result is that we need to detect those cases and make sure the
> guest sees the latest bit of data written by userland.
>
> We already have a similar mechanism when we fault pages in, but the
> guest has not enabled its caches yet.