From: Paolo Bonzini <pbonzini@redhat.com>
To: Andy Lutomirski <luto@amacapital.net>,
Marcelo Tosatti <mtosatti@redhat.com>
Cc: kvm@vger.kernel.org, Luiz Capitulino <lcapitulino@redhat.com>,
Rik van Riel <riel@redhat.com>, Radim Krcmar <rkrcmar@redhat.com>
Subject: Re: [patch 2/2] KVM: x86: add option to advance tscdeadline hrtimer expiration
Date: Thu, 11 Dec 2014 22:10:30 +0100 [thread overview]
Message-ID: <548A0846.1020406@redhat.com> (raw)
In-Reply-To: <548A0324.7070504@amacapital.net>
On 11/12/2014 21:48, Andy Lutomirski wrote:
> On 12/10/2014 07:07 PM, Marcelo Tosatti wrote:
>> On Thu, Dec 11, 2014 at 12:37:57AM +0100, Paolo Bonzini wrote:
>>>
>>>
>>> On 10/12/2014 21:57, Marcelo Tosatti wrote:
>>>> For the hrtimer which emulates the tscdeadline timer in the guest,
>>>> add an option to advance expiration, and busy spin on VM-entry waiting
>>>> for the actual expiration time to elapse.
>>>>
>>>> This allows achieving low latencies in cyclictest (or any scenario
>>>> which requires strict timing regarding timer expiration).
>>>>
>>>> Reduces cyclictest avg latency by 50%.
>>>>
>>>> Note: this option requires tuning to find the appropriate value
>>>> for a particular hardware/guest combination. One method is to measure the
>>>> average delay between apic_timer_fn and VM-entry.
>>>> Another method is to start with 1000ns, and increase the value
>>>> in say 500ns increments until avg cyclictest numbers stop decreasing.
>>>
>>> What values are you using in practice for the parameter?
>>
>> 7us.
>
> It takes 7us to get from TSC deadline expiration to the *start* of
> vmresume? That seems rather extreme.
No, to the end. 7us is 21000 clock cycles, and the vmexit+vmentry alone
costs about 1300.
> Is it possible that almost all of that latency is from deadline
> expiration to C-state exit?
No, I don't think so. Marcelo confirmed that C-states are disabled, bt
anyway none of the C-state latency matches Marcelo's data: C1 is really
small (1 us), C1e is too large (~10 us).
To see the effect of C-state exit, go to the plots I made on a normal
laptop and see latency jumping up to 200000 or 400000 cycles
(respectively 70 and 140 us, corresponding to C3 and C6 latencies of 60
and 80 us).
> If so, can we teach the timer code to wake
> up early to account for that?
What, it doesn't already do that?
Paolo
next prev parent reply other threads:[~2014-12-11 21:10 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-10 20:57 [patch 0/2] KVM: add option to advance tscdeadline hrtimer expiration (v3) Marcelo Tosatti
2014-12-10 20:57 ` [patch 1/2] KVM: x86: add method to test PIR bitmap vector Marcelo Tosatti
2014-12-10 20:57 ` [patch 2/2] KVM: x86: add option to advance tscdeadline hrtimer expiration Marcelo Tosatti
2014-12-10 23:37 ` Paolo Bonzini
2014-12-11 3:07 ` Marcelo Tosatti
2014-12-11 18:58 ` Paolo Bonzini
2014-12-11 20:48 ` Andy Lutomirski
2014-12-11 20:58 ` Marcelo Tosatti
2014-12-11 21:07 ` Andy Lutomirski
2014-12-11 21:37 ` Rik van Riel
2014-12-11 21:10 ` Paolo Bonzini [this message]
2014-12-11 21:16 ` Andy Lutomirski
2014-12-11 21:27 ` Marcelo Tosatti
2014-12-11 21:29 ` Marcelo Tosatti
2014-12-12 18:35 ` Radim Krcmar
-- strict thread matches above, loose matches on Subject: below --
2014-12-10 17:06 [patch 0/2] KVM: add option to advance tscdeadline hrtimer expiration (v2) Marcelo Tosatti
2014-12-10 17:06 ` [patch 2/2] KVM: x86: add option to advance tscdeadline hrtimer expiration Marcelo Tosatti
2014-12-10 17:11 ` Rik van Riel
2014-12-10 16:53 [patch 0/2] KVM: " Marcelo.Tosatti
2014-12-10 16:53 ` [patch 2/2] KVM: x86: " Marcelo.Tosatti
2014-12-10 17:08 ` Paolo Bonzini
2014-12-10 17:34 ` Marcelo Tosatti
2014-12-10 17:53 ` Paolo Bonzini
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