From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: Re: 2 CPU Conformance Issue in KVM/x86 Date: Mon, 09 Mar 2015 21:49:19 +0200 Message-ID: <54FDF93F.7080502@gmail.com> References: <54F58471.7020906@redhat.com> <54FDD39C.9060908@gmail.com> <6073FF8F-E261-4DC3-817A-9F4A46B5C0DB@gmail.com> <54FDE50B.8040408@gmail.com> <13DCF857-5591-4499-9B0D-4165268E9CE8@gmail.com> <54FDF241.8080002@gmail.com> <54FDF6CB.8050209@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Cc: kvm list , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= To: Paolo Bonzini , Nadav Amit Return-path: Received: from mail-wg0-f41.google.com ([74.125.82.41]:47061 "EHLO mail-wg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750741AbbCITtX (ORCPT ); Mon, 9 Mar 2015 15:49:23 -0400 Received: by wggx12 with SMTP id x12so17173128wgg.13 for ; Mon, 09 Mar 2015 12:49:22 -0700 (PDT) In-Reply-To: <54FDF6CB.8050209@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: On 03/09/2015 09:38 PM, Paolo Bonzini wrote: > > On 09/03/2015 20:19, Avi Kivity wrote: >> I can't think of one with reasonable performance either. Perhaps the >> maintainers could raise the issue with Intel. It looks academic but it >> can happen in real life -- KVM for example used to rely on reserved bits >> faults (it set all bits in the PTE so it wouldn't have been caught by >> this). > Yes, and it checked that MAXPHYADDR != 52 before. If you want to set > only one bit, making that bit 51 makes sense anyway for simplicity, so > it is still 99.9% academic. Once processors appear with MAXPHYADDR = > 52, the remaining 0.1% will become more relevant. > > The current limit is IIRC 46 or 48 (on Haswell Xeons). > It will be interesting to have processors with 52 bits of physical address and 48 bits of virtual address. HIGHMEM for x86_64? Or 5-level page tables? 50 bits == 1 PiB. That's quite an amount of RAM.