From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: 2 CPU Conformance Issue in KVM/x86 Date: Tue, 10 Mar 2015 11:47:09 +0100 Message-ID: <54FECBAD.9060809@redhat.com> References: <54F58471.7020906@redhat.com> <54FDD39C.9060908@gmail.com> <6073FF8F-E261-4DC3-817A-9F4A46B5C0DB@gmail.com> <54FDE50B.8040408@gmail.com> <13DCF857-5591-4499-9B0D-4165268E9CE8@gmail.com> <54FDF241.8080002@gmail.com> <54FDF6CB.8050209@redhat.com> <54FDF93F.7080502@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Cc: kvm list , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= To: Avi Kivity , Nadav Amit Return-path: Received: from mx1.redhat.com ([209.132.183.28]:37162 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752621AbbCJKrR (ORCPT ); Tue, 10 Mar 2015 06:47:17 -0400 In-Reply-To: <54FDF93F.7080502@gmail.com> Sender: kvm-owner@vger.kernel.org List-ID: On 09/03/2015 20:49, Avi Kivity wrote: >>> >> Yes, and it checked that MAXPHYADDR != 52 before. If you want to set >> only one bit, making that bit 51 makes sense anyway for simplicity, so >> it is still 99.9% academic. Once processors appear with MAXPHYADDR = >> 52, the remaining 0.1% will become more relevant. >> >> The current limit is IIRC 46 or 48 (on Haswell Xeons). > > It will be interesting to have processors with 52 bits of physical > address and 48 bits of virtual address. HIGHMEM for x86_64? Or 5-level > page tables? I wonder why Intel chose exactly 52... HIGHMEM seems more likely than 5-level page tables. Certainly it wouldn't need hacks like Ingo's 4G-4G. > 50 bits == 1 PiB. That's quite an amount of RAM. Not that 64 TiB is not "quite an amount of RAM". :) Paolo