From: Paolo Bonzini <pbonzini@redhat.com>
To: Nate Case <ncase@xes-inc.com>
Cc: kvm@vger.kernel.org
Subject: Re: Guest memory backed by PCI BAR (x86)
Date: Thu, 26 Mar 2015 17:40:22 +0100 [thread overview]
Message-ID: <55143676.1040709@redhat.com> (raw)
In-Reply-To: <57551226.56219.1427387686368.JavaMail.zimbra@xes-inc.com>
On 26/03/2015 17:34, Nate Case wrote:
> 0x52: add al,dh
> 0x54: pop cx
> 0x55: clc
> 0x56: add al,dh
> => 0x58: cs
> 0x59: call 0xf05c
> 0x5c: shr bh,cl
> 0x5e: add al,dh
> 0x60: add ax,0xcf
> 0x63: lock repnz out 0x0,al
This code makes no sense, it looks like the processor has gone into the
weeds. :(
Based on this:
cs 0x9020 36896
I could guess, based on your use of resource2_wc, that the host is
bypassing the processor cache but the guest is not. This use is not
supported on x86 KVM, sorry.
Paolo
next prev parent reply other threads:[~2015-03-26 16:40 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-25 15:56 Guest memory backed by PCI BAR (x86) Nate Case
2015-03-26 14:02 ` Paolo Bonzini
2015-03-26 16:01 ` Nate Case
2015-03-26 16:07 ` Paolo Bonzini
2015-03-26 16:34 ` Nate Case
2015-03-26 16:40 ` Paolo Bonzini [this message]
2015-03-26 16:52 ` Nate Case
2015-03-26 17:04 ` Paolo Bonzini
2015-03-26 17:14 ` Nate Case
2015-03-27 15:27 ` Nate Case
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