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From: Jan Kiszka <jan.kiszka@siemens.com>
To: Nadav Amit <nadav.amit@gmail.com>, Paolo Bonzini <pbonzini@redhat.com>
Cc: Avi Kivity <avi.kivity@gmail.com>, kvm list <kvm@vger.kernel.org>
Subject: Re: x86: Question regarding the reset value of LINT0
Date: Wed, 08 Apr 2015 19:51:05 +0200	[thread overview]
Message-ID: <55256A89.3030100@siemens.com> (raw)
In-Reply-To: <E6B175E1-946D-404F-8402-D0535F50C966@gmail.com>

On 2015-04-08 19:40, Nadav Amit wrote:
> Jan Kiszka <jan.kiszka@siemens.com> wrote:
> 
>> On 2015-04-08 18:59, Nadav Amit wrote:
>>> Jan Kiszka <jan.kiszka@siemens.com> wrote:
>>>
>>>> On 2015-04-08 18:40, Nadav Amit wrote:
>>>>> Hi,
>>>>>
>>>>> I would appreciate if someone explains the reason for enabling LINT0 during
>>>>> APIC reset. This does not correspond with Intel SDM Figure 10-8: “Local
>>>>> Vector Table” that says all LVT registers are reset to 0x10000.
>>>>>
>>>>> In kvm_lapic_reset, I see:
>>>>>
>>>>> 	apic_set_reg(apic, APIC_LVT0,
>>>>> 		SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
>>>>>
>>>>> Which is actually pretty similar to QEMU’s apic_reset_common:
>>>>>
>>>>>   if (bsp) {
>>>>>       /*
>>>>>        * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
>>>>>        * time typically by BIOS, so PIC interrupt can be delivered to the
>>>>>        * processor when local APIC is enabled.
>>>>>        */
>>>>>       s->lvt[APIC_LVT_LINT0] = 0x700;
>>>>>   }
>>>>>
>>>>> Yet, in both cases, I miss the point - if it is typically done by the BIOS,
>>>>> why does QEMU or KVM enable it?
>>>>>
>>>>> BTW: KVM seems to run fine without it, and I think setting it causes me
>>>>> problems in certain cases.
>>>>
>>>> I suspect it has some historic BIOS backgrounds. Already tried to find
>>>> more information in the git logs of both code bases? Or something that
>>>> indicates of SeaBIOS or BochsBIOS once didn't do this initialization?
>>> Thanks. I found no indication of such thing.
>>>
>>> QEMU’s commit message (0e21e12bb311c4c1095d0269dc2ef81196ccb60a) says:
>>>
>>>    Don't route PIC interrupts through the local APIC if the local APIC
>>>    config says so. By Ari Kivity.
>>>
>>> Maybe Avi Kivity knows this guy.
>>
>> ths? That should have been Thiemo Seufer (IIRC), but he just committed
>> the code back then (and is no longer with us, sadly).
> Oh… I am sorry - I didn’t know about that.. (I tried to make an unfunny joke
> about Avi knowing “Ari”).

Ah. No problem. My brain apparently fixed that typo up unnoticed.

> 
>> But if that commit went in without any BIOS changes around it, QEMU
>> simply had to do the job of the latter to keep things working.
> So should I leave it as is? Can I at least disable in KVM during INIT (and
> leave it as is for RESET)?

No, I don't think there is a need to leave this inaccurate for QEMU if
our included BIOS gets it right. I don't know what the backward
bug-compatibility of KVM is, though. Maybe you can identify since when
our BIOS is fine so that we can discuss time frames.

Jan

-- 
Siemens AG, Corporate Technology, CT RTC ITP SES-DE
Corporate Competence Center Embedded Linux

  reply	other threads:[~2015-04-08 17:52 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-08 16:40 x86: Question regarding the reset value of LINT0 Nadav Amit
2015-04-08 16:44 ` Jan Kiszka
2015-04-08 16:59   ` Nadav Amit
2015-04-08 17:06     ` Jan Kiszka
2015-04-08 17:40       ` Nadav Amit
2015-04-08 17:51         ` Jan Kiszka [this message]
2015-04-08 21:49           ` Nadav Amit
2015-04-08 22:11             ` Bandan Das
2015-04-09 18:21               ` Nadav Amit
2015-04-09 18:28                 ` Avi Kivity
2015-04-09 18:49                   ` Nadav Amit
2015-04-09 19:17                     ` Bandan Das
2015-04-10  9:12                       ` Paolo Bonzini
2015-04-12 18:29                         ` Nadav Amit
2015-04-12 22:53                           ` [PATCH] KVM: x86: Support for disabling quirks Nadav Amit
2015-04-13 10:34                             ` Paolo Bonzini
2015-04-13 12:02                               ` Nadav Amit

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