From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jan Kiszka Subject: Re: x86: Question regarding the reset value of LINT0 Date: Wed, 08 Apr 2015 19:51:05 +0200 Message-ID: <55256A89.3030100@siemens.com> References: <2B474EEE-85C9-47C3-89FF-C56754CFEC0D@gmail.com> <55255AF2.2070706@siemens.com> <06513D06-1629-4AC0-9014-C6D13C29A1FC@gmail.com> <55256004.8030403@siemens.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Avi Kivity , kvm list To: Nadav Amit , Paolo Bonzini Return-path: Received: from thoth.sbs.de ([192.35.17.2]:53308 "EHLO thoth.sbs.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753584AbbDHRwP (ORCPT ); Wed, 8 Apr 2015 13:52:15 -0400 In-Reply-To: Sender: kvm-owner@vger.kernel.org List-ID: On 2015-04-08 19:40, Nadav Amit wrote: > Jan Kiszka wrote: >=20 >> On 2015-04-08 18:59, Nadav Amit wrote: >>> Jan Kiszka wrote: >>> >>>> On 2015-04-08 18:40, Nadav Amit wrote: >>>>> Hi, >>>>> >>>>> I would appreciate if someone explains the reason for enabling LI= NT0 during >>>>> APIC reset. This does not correspond with Intel SDM Figure 10-8: = =E2=80=9CLocal >>>>> Vector Table=E2=80=9D that says all LVT registers are reset to 0x= 10000. >>>>> >>>>> In kvm_lapic_reset, I see: >>>>> >>>>> apic_set_reg(apic, APIC_LVT0, >>>>> SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); >>>>> >>>>> Which is actually pretty similar to QEMU=E2=80=99s apic_reset_com= mon: >>>>> >>>>> if (bsp) { >>>>> /* >>>>> * LINT0 delivery mode on CPU #0 is set to ExtInt at initia= lization >>>>> * time typically by BIOS, so PIC interrupt can be delivere= d to the >>>>> * processor when local APIC is enabled. >>>>> */ >>>>> s->lvt[APIC_LVT_LINT0] =3D 0x700; >>>>> } >>>>> >>>>> Yet, in both cases, I miss the point - if it is typically done by= the BIOS, >>>>> why does QEMU or KVM enable it? >>>>> >>>>> BTW: KVM seems to run fine without it, and I think setting it cau= ses me >>>>> problems in certain cases. >>>> >>>> I suspect it has some historic BIOS backgrounds. Already tried to = find >>>> more information in the git logs of both code bases? Or something = that >>>> indicates of SeaBIOS or BochsBIOS once didn't do this initializati= on? >>> Thanks. I found no indication of such thing. >>> >>> QEMU=E2=80=99s commit message (0e21e12bb311c4c1095d0269dc2ef81196cc= b60a) says: >>> >>> Don't route PIC interrupts through the local APIC if the local A= PIC >>> config says so. By Ari Kivity. >>> >>> Maybe Avi Kivity knows this guy. >> >> ths? That should have been Thiemo Seufer (IIRC), but he just committ= ed >> the code back then (and is no longer with us, sadly). > Oh=E2=80=A6 I am sorry - I didn=E2=80=99t know about that.. (I tried = to make an unfunny joke > about Avi knowing =E2=80=9CAri=E2=80=9D). Ah. No problem. My brain apparently fixed that typo up unnoticed. >=20 >> But if that commit went in without any BIOS changes around it, QEMU >> simply had to do the job of the latter to keep things working. > So should I leave it as is? Can I at least disable in KVM during INIT= (and > leave it as is for RESET)? No, I don't think there is a need to leave this inaccurate for QEMU if our included BIOS gets it right. I don't know what the backward bug-compatibility of KVM is, though. Maybe you can identify since when our BIOS is fine so that we can discuss time frames. Jan --=20 Siemens AG, Corporate Technology, CT RTC ITP SES-DE Corporate Competence Center Embedded Linux