From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [Qemu-devel][PATCH 1/2] target-i386: disable LINT0 after reset Date: Mon, 13 Apr 2015 16:12:45 +0200 Message-ID: <552BCEDD.9040405@redhat.com> References: <1428881529-29459-1-git-send-email-namit@cs.technion.ac.il> <1428881529-29459-2-git-send-email-namit@cs.technion.ac.il> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Cc: kvm@vger.kernel.org, qemu-devel@nongnu.org, jan.kiszka@siemens.com, bsd@redhat.com, avi.kivity@gmail.com To: Nadav Amit Return-path: Received: from mx1.redhat.com ([209.132.183.28]:45095 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752946AbbDMONC (ORCPT ); Mon, 13 Apr 2015 10:13:02 -0400 In-Reply-To: <1428881529-29459-2-git-send-email-namit@cs.technion.ac.il> Sender: kvm-owner@vger.kernel.org List-ID: On 13/04/2015 01:32, Nadav Amit wrote: > Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone > and therefore this hack is no longer needed. Since it violates the > specifications, it is removed. > > Signed-off-by: Nadav Amit > --- > hw/intc/apic_common.c | 9 --------- > 1 file changed, 9 deletions(-) > > diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c > index 042e960..d38d24b 100644 > --- a/hw/intc/apic_common.c > +++ b/hw/intc/apic_common.c > @@ -243,15 +243,6 @@ static void apic_reset_common(DeviceState *dev) > info->vapic_base_update(s); > > apic_init_reset(dev); > - > - if (bsp) { > - /* > - * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization > - * time typically by BIOS, so PIC interrupt can be delivered to the > - * processor when local APIC is enabled. > - */ > - s->lvt[APIC_LVT_LINT0] = 0x700; > - } > } > > /* This function is only used for old state version 1 and 2 */ > Thanks, applied this one. The other will have to wait for a bit, since it depends on a patch that is destined to Linux 4.2. Paolo