From mboxrd@z Thu Jan 1 00:00:00 1970 From: Xiao Guangrong Subject: Re: [PATCH 14/15] KVM: MTRR: do not map huage page for non-consistent range Date: Thu, 04 Jun 2015 16:26:55 +0800 Message-ID: <55700BCF.1010703@linux.intel.com> References: <1432983566-15773-1-git-send-email-guangrong.xiao@linux.intel.com> <1432983566-15773-15-git-send-email-guangrong.xiao@linux.intel.com> <556C27A5.1040908@redhat.com> <556E6CF8.9070602@linux.intel.com> <556EB30F.8030100@redhat.com> <55700B0D.8080808@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Cc: gleb@kernel.org, mtosatti@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org To: Paolo Bonzini Return-path: In-Reply-To: <55700B0D.8080808@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On 06/04/2015 04:23 PM, Xiao Guangrong wrote: > > > On 06/03/2015 03:55 PM, Paolo Bonzini wrote: >> >> >> On 03/06/2015 04:56, Xiao Guangrong wrote: >>> >>> >>> On 06/01/2015 05:36 PM, Paolo Bonzini wrote: >>>> >>>> >>>> On 30/05/2015 12:59, Xiao Guangrong wrote: >>>>> Currently guest MTRR is completely prohibited if cache snoop is >>>>> supported on >>>>> IOMMU (!noncoherent_dma) and host does the emulation based on the >>>>> knowledge >>>>> from host side, however, host side is not the good point to know >>>>> what the purpose of guest is. A good example is that pass-throughed VGA >>>>> frame buffer is not always UC as host expected >>>> >>>> Can you explain how? The original idea was that such a framebuffer >>>> would be kvm_is_reserved_pfn and thus be unconditionally UC. >>> >>> Yes, frame-buffer is always UC in current code, however, UC for >>> frame-buffer causes bad performance. >> >> Understood now, thanks. >> >>> So that guest will configure the range to MTRR, this patchset follows >>> guest MTRR and cooperates with guest PAT (ept.VMX_EPT_IPAT_BIT = 0) to >>> emulate guest cache type as guest expects. >> >> Unlike e.g. CR0.CD=1, UC memory does not snoop the cache to preserve >> coherency. AMD, has special logic to do this, for example: >> >> - if guest PAT says "UC" and host MTRR says "WB", the processor will not >> cache the memory but will snoop the cache as if CR0.CD=1 >> >> - if guest PAT says "WC" and host (nested page table) PAT says "WB" and >> host MTRR says "WB", the processor will still do write combining but >> also snoop the cache as if CR0.CD=1 >> >> I am worried that the lack of this feature could cause problems if >> guests map QEMU's VGA framebuffer as uncached. We have this problem on >> ARM, so it's not 100% theoretical. > > CR0.CD is always 0 in both host and guest, i guess it's why we cleared > CR0.CD and CR0.NW in vmx_set_cr0(). It reminds me that we should check guest CR0.CD before check guest MTRR and disable guest PAT if guest CR0.CD = 1.