From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH v2 12/13] KVM: x86: add SMM to the MMU role, support SMRAM address space Date: Thu, 18 Jun 2015 09:02:41 +0200 Message-ID: <55826D11.2060801@redhat.com> References: <1432746314-50196-1-git-send-email-pbonzini@redhat.com> <1432746314-50196-13-git-send-email-pbonzini@redhat.com> <55766510.7010108@linux.intel.com> <55812D4F.10506@redhat.com> <558250D4.3050505@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Cc: rkrcmar@redhat.com, bdas@redhat.com To: Xiao Guangrong , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Return-path: Received: from mail-wg0-f45.google.com ([74.125.82.45]:35849 "EHLO mail-wg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750954AbbFRHCo (ORCPT ); Thu, 18 Jun 2015 03:02:44 -0400 In-Reply-To: <558250D4.3050505@linux.intel.com> Sender: kvm-owner@vger.kernel.org List-ID: On 18/06/2015 07:02, Xiao Guangrong wrote: > However, role->level is more hotter than role->smm so that it's also a good > candidate for this kind of trick. Right, we could give the first 8 bits to role->level, so it can be accessed with a single memory load and extracted with a single AND. Those two are definitely the hottest fields. > And this is only 32 bits which can be operated in a CPU register by a > single memory load, that is why i was worried if it is really needed. However, an 8-bit field can be loaded from memory with a single movz instruction. Paolo