From: Paolo Bonzini <pbonzini@redhat.com>
To: "Zhang, Yang Z" <yang.z.zhang@intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Cc: "alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"srutherford@intel.com" <srutherford@intel.com>
Subject: Re: [PATCH 1/2] KVM: x86: set TMR when the interrupt is accepted
Date: Fri, 31 Jul 2015 10:01:38 +0200 [thread overview]
Message-ID: <55BB2B62.1030605@redhat.com> (raw)
In-Reply-To: <A9667DDFB95DB7438FA9D7D576C3D87E0AD5A4E1@SHSMSX104.ccr.corp.intel.com>
On 31/07/2015 01:26, Zhang, Yang Z wrote:
>>> Do not compute TMR in advance. Instead, set the TMR just before
>>> the interrupt is accepted into the IRR. This limits the coupling
>>> between IOAPIC and LAPIC.
>
> Uh.., it back to original way which is wrong. You cannot modify the
> apic page(here is the TMR reg) directly when the corresponding VMCS
> may be used at same time.
Where is this documented? The TMR is not part of the set of virtualized
APIC registers (TPR, PPR, EOI, ISR, IRR, ICR+ICR2; SDM 29.1.1).
Only virtualized APIC register reads use the virtual TMR registers (SDM
29.4.2 or 29.5), but these just read data from the corresponding field
in the virtual APIC page.
Paolo
next prev parent reply other threads:[~2015-07-31 8:01 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-29 13:37 [PATCH 0/2] KVM: x86: limit interactions between IOAPIC and LAPIC Paolo Bonzini
2015-07-29 13:37 ` [PATCH 1/2] KVM: x86: set TMR when the interrupt is accepted Paolo Bonzini
2015-07-30 3:39 ` Steve Rutherford
2015-07-30 23:26 ` Zhang, Yang Z
2015-07-31 2:49 ` Steve Rutherford
2015-07-31 7:57 ` Paolo Bonzini
2015-08-03 2:44 ` Zhang, Yang Z
2015-07-31 8:01 ` Paolo Bonzini [this message]
2015-08-03 2:37 ` Zhang, Yang Z
2015-08-03 8:10 ` Paolo Bonzini
2015-08-03 10:23 ` Zhang, Yang Z
2015-08-03 10:55 ` Paolo Bonzini
2015-08-04 0:46 ` Zhang, Yang Z
2015-08-04 6:59 ` Paolo Bonzini
2015-08-04 7:21 ` Zhang, Yang Z
2015-08-13 6:35 ` Zhang, Yang Z
2015-08-13 7:31 ` Paolo Bonzini
2015-09-02 22:38 ` Steve Rutherford
2015-09-03 5:18 ` Nakajima, Jun
2015-09-03 7:38 ` Paolo Bonzini
2015-07-29 13:37 ` [PATCH 2/2] KVM: x86: store IOAPIC-handled vectors in each VCPU Paolo Bonzini
2015-07-30 3:55 ` Steve Rutherford
2015-07-30 7:19 ` Paolo Bonzini
2015-07-29 20:00 ` [PATCH 0/2] KVM: x86: limit interactions between IOAPIC and LAPIC Alex Williamson
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