Re: [PATCH v3] KVM: x86: INIT and reset sequences are different

[Paolo Bonzini <pbonzini@redhat.com>]

On 13/04/2015 13:34, Nadav Amit wrote:
> x86 architecture defines differences between the reset and INIT sequences.
> INIT does not initialize the FPU (including MMX, XMM, YMM, etc.), TSC, PMU,
> MSRs (in general), MTRRs machine-check, APIC ID, APIC arbitration ID and BSP.
> 
> References (from Intel SDM):
> 
> "If the MP protocol has completed and a BSP is chosen, subsequent INITs (either
> to a specific processor or system wide) do not cause the MP protocol to be
> repeated." [8.4.2: MP Initialization Protocol Requirements and Restrictions]
> 
> [Table 9-1. IA-32 Processor States Following Power-up, Reset, or INIT]
> 
> "If the processor is reset by asserting the INIT# pin, the x87 FPU state is not
> changed." [9.2: X87 FPU INITIALIZATION]
> 
> "The state of the local APIC following an INIT reset is the same as it is after
> a power-up or hardware reset, except that the APIC ID and arbitration ID
> registers are not affected." [10.4.7.3: Local APIC State After an INIT Reset
> (“Wait-for-SIPI” State)]
> 
> Signed-off-by: Nadav Amit <namit@cs.technion.ac.il>
> 
> ---
> 
> v3:
> 
> - Leave EFER unchanged on INIT. Instead, set cr0 correctly so vmx_set_cr0 would
>   recognize that paging was changed from on to off and clear LMA.

I wonder if this change from v2 to v3 was correct.

It means that a 32-bit firmware cannot enter paging mode without
clearing EFER.LME first (which it should not know about).

Yang, can you check what real hardware does to EFER on an INIT?  Perhaps
it only clears EFER.LME (in addition of course to EFER.LMA, which is
cleared as a side effect of writing CR0).

Thanks,

Paolo